Epson S1D13504 ユーザーズマニュアル

Epson Research and Development

Page 61

Vancouver Design Center

Programming Notes and Examples

S1D13504

Issue Date: 01/02/01

X19A-G-002-07

Appendix A Supported Panel Values

A.1 Supported Panel Values

The following tables show related register data for different panels. All the examples are based on
8 bpp, 40MHz pixel clock and 2M bytes of 60 ns EDO-DRAM.

Table 9-1: Passive Single Panel

Register

Passive

4-Bit Single

320X240@60Hz

Monochrome

Passive

8-Bit Single

320X240@60Hz

Color

Passive

8-Bit Single

640X480@60Hz

Monochrome

Passive

8-Bit Single

640X480@60Hz

Color

Passive

16-Bit Single

640X480@47Hz

Color

Notes

REG[02h]

0000 0000

0001 0100

0001 0000

0001 0100

0010 0100

set panel type

REG[03h]

0000 0000

set MOD rate

REG[04h]

0010 0111

0100 1111

set horizontal display width

REG[05h]

0001 0000

0000 0101

set horizontal non-display period

REG[08h]

1110 1111

1101 1111

set vertical display height bits 7-0

REG[09h]

0000 0000

0000 0001

set vertical display height bits 9-8

REG[0Ah]

0000 0001

set vertical non-display period

REG[0Dh]

0000 1101

set 8 bpp and LCD enable

REG[19h]

0000 0110

0000 0001

set MCLK and PCLK divide

REG[24h]

0000 0000

set Look-Up Table address to 0

REG[26h]

load LUT

load Look-Up Table

REG[27h]

0000 0000

set Look-Up Table to bank 0

Table 9-2: Passive Dual Panel

Register

Passive

8-Bit Dual

640X480@60Hz

Monochrome

Passive

8-Bit Dual

640X480@60Hz

Color

Passive

16-Bit Dual

640X480@60Hz

Color

Notes

REG[02h]

0001 0010

0001 0110

0010 0110

set panel type

REG[03h]

0000 0000

set MOD rate

REG[04h]

0100 1111

set horizontal display width

REG[05h]

0000 0101

set horizontal non-display period

REG[08h]

1110 1111

set vertical display height bits 7-0

REG[09h]

0000 0000

set vertical display height bits 9-8

REG[0Ah]

0000 0001

set vertical non-display period

REG[0Dh]

0000 1101

set 8 bpp and LCD enable

REG[19h]

0000 0011

set MCLK and PCLK divide

REG[1Bh]

0000 0000

enable half frame buffer

REG[24h]

0000 0000

set Look-Up Table address to 0

REG[26h]

load LUT

load Look-Up Table

REG[27h]

0000 0000

set Look-Up Table to bank 0