Epson S1D13504 ユーザーズマニュアル

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Epson Research and Development
Vancouver Design Center
S1D13504
Programming Notes and Examples
X19A-G-002-07
Issue Date: 01/02/01
Table 9-3: TFT Panel
Register
TFT 16-Bit 
Single
 
640X480@47Hz 
Color
Notes
REG[02h]
0010 0101
set panel type
REG[03h]
0000 0000
set MOD rate
REG[04h]
0100 1111
set horizontal display width
REG[05h]
0001 0011
set horizontal non-display period
REG[06h]
0000 0110
set HSYNC start position
REG[07h]
0000 0111
set HSYNC polarity and pulse width
REG[08h]
1101 1111
set vertical display height bits 7-0
REG[09h]
0000 0001
set vertical display height bits 9-8
REG[0Ah]
0010 1101
set vertical non-display period
REG[0Bh]
0000 0000
set VSYNC start position
REG[0Ch]
0000 0010
set VSYNC polarity and pulse width
REG[0Dh]
0000 1101
set 8 bpp and LCD enable
REG[19h]
0000 0001
set MCLK and PCLK divide
REG[24h]
0000 0000
set Look-Up Table address to 0
REG[26h]
load LUT
load Look-Up Table
REG[27h]
0000 0000
set Look-Up Table to bank 0