Epson S1D13504 ユーザーズマニュアル
Epson Research and Development
Page 31
Vancouver Design Center
Hardware Functional Specification
S1D13504
Issue Date: 01/01/30
X19A-A-002-18
5.5 Summary of Configuration Options
Table 5-8: Summary of Power On / Reset Options
Pin Name
value on this pin at rising edge of RESET# is used to configure:
(1/0)
1
0
MD0
8-bit host bus interface
16-bit host bus interface
MD[3:1]
Select host bus interface:
000 =
SH-3
bus
interface
001 =
MC68K
bus
1
(e.g.
MC68000)
010 =
MC68K
bus
2
(e.g.
MC68030)
011 = Generic bus interface (e.g. Philips MIPS PR31500/PR31700; NEC MIPS V
R
4102)
1XX =
reserved
MD4
Little Endian
Big Endian
MD5
WAIT# is active high (1 = insert wait state)
WAIT# is active low (0 = insert wait state)
MD[7:6]
Memory Address/GPIO configuration:
00 =
symmetrical
256K
×
16 DRAM. MA[8:0]
= DRAM address. MA[11:9]
= GPIO[2:1] and GPIO3.
01 = symmetrical 1M
×
16 DRAM.
MA[9:0]
= DRAM address. MA[11:10]
= GPIO[2:1].
10 = asymmetrical 256K
×
16 DRAM. MA[9:0]
= DRAM address. MA[11:10]
= GPIO[2:1].
11 = asymmetrical 1M
×
16 DRAM.
MA[11:0] = DRAM address.
MD8
Configure DACRD#, BLANK#, DACP0, DACWR#,
DACRS0, DACRS1, HRTC, VRTC as General
Purpose IO (GPIO[11:4]).
DACRS0, DACRS1, HRTC, VRTC as General
Purpose IO (GPIO[11:4]).
Configure DACRD#, BLANK#, DACP0, DACWR#,
DACRS0, DACRS1, HRTC, VRTC as DAC and CRT
outputs.
DACRS0, DACRS1, HRTC, VRTC as DAC and CRT
outputs.
MD9
SUSPEND# pin configured as GPO output.
SUSPEND# pin configured as SUSPEND# input.
MD10
Active low LCDPWR or GPO polarities.
Active high LCDPWR or GPO polarities.
MD[15:11]
Not used.