Epson S1D13504 ユーザーズマニュアル
Epson Research and Development
Page 11
Vancouver Design Center
Interfacing to the Philips MIPS PR31500/PR31700 Processor
S1D13504
Issue Date: 01/02/02
X19A-G-005-08
4 Direct Connection to the Philips PR31500/PR31700
4.1 Hardware Description
The S1D13504 is easily interfaced to the Philips PR31500/PR31700 processor. In the direct
connection implementation, the S1D13504 occupies PC Card slot #1 of the
PR31500/PR31700. Although the address bus of the PR31500/PR31700 is multiplexed, it
can be demultiplexed using an advanced CMOS latch (e.g., 74ACT373). The direct
connection implementation makes use of the Generic MPU host bus interface capability of
the S1D13504.
connection implementation, the S1D13504 occupies PC Card slot #1 of the
PR31500/PR31700. Although the address bus of the PR31500/PR31700 is multiplexed, it
can be demultiplexed using an advanced CMOS latch (e.g., 74ACT373). The direct
connection implementation makes use of the Generic MPU host bus interface capability of
the S1D13504.
The following diagram demonstrates a typical implementation of the PR31500/PR31700 to
S1D13504 interface.
S1D13504 interface.
Figure 4-1: Typical Implementation of S1D13504 to PR31500/PR31700 Direct Connection
Note
For pin mapping see Table 3-1:, “Generic MPU Host Bus Interface Pin Mapping”.
RD1#
RD0#
DB[7:0]
WAIT#
BUSCLK
S1D13504
RESET#
AB[20:13]
/RD
D[31:24]
/CARD1WAIT
A[12:0]
PR31500/PR31700
15K pull-up
CLKI
Oscillator
WE1#
WE0#
M/R#
CS#
/WE
/CARD1CSL
/CARD1CSH
A23
Latch
ALE
System RESET
A[20:13]
AB[12:0]
ENDIAN
DB[15:8]
D[23:16]
V
DD
DCLKOUT
...or...
Clock divider
See text
IO V
DD
, CORE V
DD
+3.3V
Note:
When connecting the S1D13504 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13504 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
When connecting the S1D13504 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13504 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).