Epson S1D13504 ユーザーズマニュアル
Page 12
Epson Research and Development
Vancouver Design Center
S1D13504
Interfacing to the Philips MIPS PR31500/PR31700 Processor
X19A-G-005-08
Issue Date: 01/02/02
The host interface control signals of the S1D13504 are asynchronous with respect to the
S1D13504 bus clock. This gives the system designer full flexibility in choosing the appro-
priate source (or sources) for CLKI and BUSCLK. Deciding whether both clocks should be
the same and whether to use DCLKOUT (divided) as the clock source, should be based on
the desired:
S1D13504 bus clock. This gives the system designer full flexibility in choosing the appro-
priate source (or sources) for CLKI and BUSCLK. Deciding whether both clocks should be
the same and whether to use DCLKOUT (divided) as the clock source, should be based on
the desired:
• pixel and frame rates.
• power budget.
• part count.
• maximum S1D13504 clock frequencies.
The S1D13504 also has internal clock dividers providing additional flexibility.
4.2 Memory Mapping and Aliasing
The S1D13504 requires an addressing space of 2M bytes for the display buffer and 64 bytes
for the registers. This is divided into two address ranges by connecting A23 (demultiplexed
from the PR31500/PR31700) to the M/R# input of the S1D13504. Using A23 makes this
implementation software compatible with the two implementations that use the ITE
IT8368E (see Section 5, “System Design Using the IT8368E PC Card Buffer” on page 14).
All other addresses are ignored.
for the registers. This is divided into two address ranges by connecting A23 (demultiplexed
from the PR31500/PR31700) to the M/R# input of the S1D13504. Using A23 makes this
implementation software compatible with the two implementations that use the ITE
IT8368E (see Section 5, “System Design Using the IT8368E PC Card Buffer” on page 14).
All other addresses are ignored.
The S1D13504 address ranges, as seen by the PR31500/PR31700 on the PC Card slot 1
memory space, are as follows:
memory space, are as follows:
• 6400 0000h: S1D13504 registers aliased 131,072 times at 64 byte intervals over 8M
bytes.
• 6480 0000h: S1D13504 display buffer aliased 4 times at 2M byte intervals over 8M
bytes.
• 6500 0000h: S1D13504 registers and display buffer, aliased another 3 times over 48M
bytes.
Since the PR31500/PR31700 control signal /CARDREG is ignored, the S1D13504 takes
up the entire PC Card slot 1 configuration space. The address range is software compatible
with both ITE IT8368E implementations.
up the entire PC Card slot 1 configuration space. The address range is software compatible
with both ITE IT8368E implementations.
• 0900 0000h: S1D13504 registers aliased 131,072 times at 64 byte intervals over 8M
bytes.
• 0980 0000h: S1D13504 display buffer aliased 4 times at 2M byte intervals over 8M
bytes.
Note
If aliasing is undesirable, additional decoding circuitry must be added.