Epson S1D13504 ユーザーズマニュアル
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Epson Research and Development
Vancouver Design Center
S1D13504
Interfacing to the Philips MIPS PR31500/PR31700 Processor
X19A-G-005-08
Issue Date: 01/02/02
5 System Design Using the IT8368E PC Card Buffe r
If the system designer uses an ITE IT8368E PC Card and multiple-function IO buffer, the
S1D13504 can be interfaced with the PR31500/PR31700 without using a PC Card slot.
Instead, the S1D13504 is mapped to a rarely-used 16M byte portion of the PC Card slot
buffered by the IT8368E. This makes the S1D13504 virtually transparent to PC Card
devices that use the same slot.
S1D13504 can be interfaced with the PR31500/PR31700 without using a PC Card slot.
Instead, the S1D13504 is mapped to a rarely-used 16M byte portion of the PC Card slot
buffered by the IT8368E. This makes the S1D13504 virtually transparent to PC Card
devices that use the same slot.
5.1 Hardware Description—Using One IT8368E
The ITE IT8368E has been specifically designed to support EPSON LCD/CRT controllers.
The IT8368E provides eleven Multi-Function IO pins (MFIO). Configuration registers can
be used to allow these MFIO pins to provide the control signals required to implement the
S1D13504 CPU interface.
The IT8368E provides eleven Multi-Function IO pins (MFIO). Configuration registers can
be used to allow these MFIO pins to provide the control signals required to implement the
S1D13504 CPU interface.
The Philips PR31500/PR31700 processor only provides addresses A[12:0], therefore
devices that occupy more address space must use an external device to latch A[25:13]. The
IT8368E’s MFIO pins can be configured to provide this latched address. However, when
using the S1D13504, five MFIO pins are utilized for S1D13504 control signals and cannot
provide latched addresses. In this case, an external latch must be used to provide the high-
order address bits. For a solution that does not require a latch, refer to Section 5.2,
‘Hardware Description—Using Two IT8368E’s”.
devices that occupy more address space must use an external device to latch A[25:13]. The
IT8368E’s MFIO pins can be configured to provide this latched address. However, when
using the S1D13504, five MFIO pins are utilized for S1D13504 control signals and cannot
provide latched addresses. In this case, an external latch must be used to provide the high-
order address bits. For a solution that does not require a latch, refer to Section 5.2,
‘Hardware Description—Using Two IT8368E’s”.