Epson S1D13504 ユーザーズマニュアル
Epson Research and Development
Page 9
Vancouver Design Center
Interfacing to the NEC VR4102™ Microprocessor
S1D13504
Issue Date: 01/02/02
X19A-G-007-07
2.1.2 LCD Memory Access Cycles
Once an address in the LCD block of memory is placed on the external address bus
(ADD[25:0]), the LCD chip select (LCDCS#) is driven low. The read or write enable
signals (RD# or WR#) are driven low for the appropriate cycle and LCDRDY is driven low
to insert wait states into the cycle. The high byte enable (SHB#) is driven low for 16-bit
transfers and high for 8-bit transfers.
(ADD[25:0]), the LCD chip select (LCDCS#) is driven low. The read or write enable
signals (RD# or WR#) are driven low for the appropriate cycle and LCDRDY is driven low
to insert wait states into the cycle. The high byte enable (SHB#) is driven low for 16-bit
transfers and high for 8-bit transfers.
The following figure illustrates typical NEC VR4102 memory read and write cycles to the
LCD controller interface.
LCD controller interface.
Figure 2-1: NEC VR4102 Read/Write Cycles
TCLK
ADD[25:0]
LCDCS#
WR#,RD#
LCDRDY
VALID
VALID
VALID
Hi-Z
Hi-Z
D[15:0]
D[15:0]
(write)
(read)
SHB#