Epson S1D13504 ユーザーズマニュアル
Epson Research and Development
Page 9
Vancouver Design Center
Interfacing to the Motorola MC68328 "Dragonball" Microprocessor
S1D13504
Issue Date: 01/02/02
X19A-G-013-02
3 S1D13504 Host Bus Interface
This section is summary of the bus interface modes available on the S1D13504, and offers
some detail on the Generic MPU host bus interface used to implement the interface to the
MC68328.
some detail on the Generic MPU host bus interface used to implement the interface to the
MC68328.
The Generic MPU host bus interface is selected by the S1D13504 on the rising edge of
RESET#. After releasing reset the bus interface signals assume their selected configuration.
RESET#. After releasing reset the bus interface signals assume their selected configuration.
Note
After reset, the Host Interface Disable bit in the Miscellaneous Disable Register
(REG[1Bh]) will be set to logic ‘1’, meaning that the S1D13504 will not respond to any
host accesses until a write to REG[1Bh] clears this bit to 0. When debugging a new
hardware design, this can sometimes give the appearance that the interface is not work-
ing, so it is important to remember to clear this bit before proceeding with debugging.
(REG[1Bh]) will be set to logic ‘1’, meaning that the S1D13504 will not respond to any
host accesses until a write to REG[1Bh] clears this bit to 0. When debugging a new
hardware design, this can sometimes give the appearance that the interface is not work-
ing, so it is important to remember to clear this bit before proceeding with debugging.
3.1 Generic MPU Host Bus Interface Pin Mapping
The following table shows the functions of each host bus interface signal.
Table 3-1: Generic MPU Host Bus Interface Pin Mapping
S1D13504
Pin Names
Generic MPU
AB[20:1]
A[20:1]
AB0
A0
DB[15:0]
D[15:0]
WE1#
WE1#
M/R#
External Decode
CS#
External Decode
BUSCLK
BCLK
BS#
Connect to IO V
DD
RD/WR#
RD1#
RD#
RD0#
WE0#
WE0#
WAIT#
WAIT#
RESET#
RESET#