Epson S1D13504 ユーザーズマニュアル
Epson Research and Development
Page 11
Vancouver Design Center
Interfacing to the Motorola MC68328 "Dragonball" Microprocessor
S1D13504
Issue Date: 01/02/02
X19A-G-013-02
4 MC68328 To S1D13504 Interface
4.1 Hardware Description
As mentioned earlier in this application note, the MC68328 multiplexes dual functions on
some of its bus control pins, specifically UDS, LDS, and DTACK. If all of these pins are
available for use as bus control pins, then the S1D13504 interface is a straightforward
implementation of the MC68000 Bus 1 interface mode as described in the S1D13504
Hardware Functional Specification, document number X19A-A-002-xx. Following are the
electrical connections required for this interface.
some of its bus control pins, specifically UDS, LDS, and DTACK. If all of these pins are
available for use as bus control pins, then the S1D13504 interface is a straightforward
implementation of the MC68000 Bus 1 interface mode as described in the S1D13504
Hardware Functional Specification, document number X19A-A-002-xx. Following are the
electrical connections required for this interface.
Figure 4-1: Block Diagram of MC68328 to S1D13504 Interface - MC68000 Bus 1 Interface Mode
MC68328
S1D13504
A[20:1]
D[15:0]
DTACK
UDS
LDS
R/W
CLK0
AB[20:1]
SD[15:0]
CS#
WAIT#
WE1#
AB0
RD1#
RD0#
BUSCLK
RESET#
Vcc
470
A21
M/R#
CSB3
AS
BS#
Vcc
Note:
When connecting the S1D13504 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13504 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
When connecting the S1D13504 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13504 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
System RESET