Epson S1D13504 ユーザーズマニュアル
Page 12
Epson Research and Development
Vancouver Design Center
S1D13504
Interfacing to the PC Card Bus
X19A-G-009-05
Issue Date: 01/02/02
4 PC Card to S1D13504 Interface
4.1 Hardware Description
The S1D13504 is interfaced to the PC Card bus with a minimal amount of glue logic. A
PAL is used to decode the read and write signals of the PC Card bus which generate RD#,
RD/WR#, WE0#, WE1#, and CS# for the S1D13504. The PAL also inverts the reset signal
of the PC card since it is active high and the S1D13504 uses an active low reset. PAL
equations for this implementation are listed in Section 4.3,“PAL Equations” on page 14.
PAL is used to decode the read and write signals of the PC Card bus which generate RD#,
RD/WR#, WE0#, WE1#, and CS# for the S1D13504. The PAL also inverts the reset signal
of the PC card since it is active high and the S1D13504 uses an active low reset. PAL
equations for this implementation are listed in Section 4.3,“PAL Equations” on page 14.
In this implementation, the address inputs (AB[20:0]) and data bus (DB[15:0] connect
directly to the CPU address (A[20:0]) and data bus (D[15:0]). M/R# is treated as an address
line so that it can be controlled using system address A21. BS# (bus start) is not used and
should be tied low (connected to GND).
directly to the CPU address (A[20:0]) and data bus (D[15:0]). M/R# is treated as an address
line so that it can be controlled using system address A21. BS# (bus start) is not used and
should be tied low (connected to GND).
The PC Card interface does not provide a bus clock, so one must be supplied for the
S1D13504. Since the bus clock frequency is not critical, nor does it have to be synchronous
to the bus signals, it may be the same as CLKI.
S1D13504. Since the bus clock frequency is not critical, nor does it have to be synchronous
to the bus signals, it may be the same as CLKI.
The following diagram shows a typical implementation of the PC Card to S1D13504
interface.
interface.
Figure 4-1: Typical Implementation of PC Card to S1D13504 Interface
Note
For pin mapping see Table 3-1: “Generic MPU Host Bus Interface Pin Mapping”.
RD/WR#
RD#
DB[15:0]
WAIT#
BUSCLK
S1D13504
RESET#
AB[20:0]
OE#
D[15:0]
WAIT#
A[21:0]
PC Card
15K pull-up
PAL16L8-10
CLKI
Oscillator
WE1#
WE0#
M/R#
CS#
WE#
CE1#
CE2#
CE2#
REG#
RESET
A21
Note:
When connecting the S1D13504 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13504 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
When connecting the S1D13504 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13504 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).