Epson S1D13504 ユーザーズマニュアル
Page 14
Epson Research and Development
Vancouver Design Center
S1D13504
Interfacing to the PC Card Bus
X19A-G-009-05
Issue Date: 01/02/02
4.3 PAL Equations
The PAL equations used for the implementation presented in this document are as follows.
Note that PALASM syntax uses positive logic. Active low pins are inverted in the pin
declaration section.
Note that PALASM syntax uses positive logic. Active low pins are inverted in the pin
declaration section.
CHIP PCCAPP PAL16L8
PIN 1 /oe COMBINATORIAL ; bus read enable
PIN 2 /we COMBINATORIAL ; bus write enable
PIN 3 /ce1 COMBINATORIAL ; bus low byte enable
PIN 4 /ce2 COMBINATORIAL ; bus high byte enable
PIN 5 /pcreg COMBINATORIAL ; bus CIS cycle enable
PIN 6 breset COMBINATORIAL ; bus reset (active high)
PIN 12 /we0 COMBINATORIAL ; S1D13504 low byte write
PIN 13 /we1 COMBINATORIAL ; S1D13504 high byte write
PIN 14 /cs COMBINATORIAL ; S1D13504 chip select
PIN 15 /rd0 COMBINATORIAL ; S1D13504 low byte read
PIN 16 /rd1 COMBINATORIAL ; S1D13504 high byte read
PIN 17 /reset COMBINATORIAL ; S1D13504 reset
PIN 10 gnd ; supply
PIN 20 vcc ; supply
EQUATIONS
rd0 = oe * ce1 * /pcreg ; /pcreg means disable in attribute mode
rd1 = oe * ce2 * /pcreg ; /pcreg means disable in attribute mode
we0 = we * ce1 * /pcreg ; /pcreg means disable in attribute mode
we1 = we * ce2 * /pcreg ; /pcreg means disable in attribute mode
cs = rd0 + rd1 + we0 + we1
reset = breset ; inversion appears in pin declaration section
4.4 Register/Memory Mapping
The S1D13504 is a memory mapped device. The internal registers are mapped in the lower
PC Card memory address space starting at zero. The display buffer requires 2M bytes and
is mapped in the third and fourth megabytes of the PC Card memory address space (ranging
from 200000h to 3fffffh).
PC Card memory address space starting at zero. The display buffer requires 2M bytes and
is mapped in the third and fourth megabytes of the PC Card memory address space (ranging
from 200000h to 3fffffh).
The PC Card socket provides 64M bytes of address space. Without further resolution on
the decoding logic (M/R# connected to A21), the entire register set is aliased for every 64
byte boundary within the specified address range above. Since address bits A[25:22] are
ignored, the S1D13505 registers and display buffer are aliased 16 times.
the decoding logic (M/R# connected to A21), the entire register set is aliased for every 64
byte boundary within the specified address range above. Since address bits A[25:22] are
ignored, the S1D13505 registers and display buffer are aliased 16 times.
Note
If aliasing is not desirable, the upper addresses must be fully decoded.