Epson S1D13504 ユーザーズマニュアル
Epson Research and Development
Page 63
Vancouver Design Center
Hardware Functional Specification
S1D13504
Issue Date: 01/01/30
X19A-A-002-18
7.4 Display Interface
7.4.1 Power-On/Reset Timing
Figure 7-17: LCD Panel Power-On/Reset Timing
Note
Where T
FPFRAME
is the period of FPFRAME and T
PCLK
is the period of the pixel clock.
Table 7-17: LCD Panel Power-On/Reset Timing
Symbol
Parameter
Min
Typ
Max
Units
T
RESET#
RESET# pulse time
100
us
t1
LCD Enable bit high to FPLINE, FPSHIFT, FPDAT[15:0], DRDY
active
active
T
FPFRAME
+ 6T
PCLK
ns
t2
FPLINE, FPSHIFT, FPDAT[15:0], DRDY active to LCDPWR, on
and FPFRAME active
and FPFRAME active
128
Frames
RESET#
LCD ENABLE
LCDPWR
FPFRAME
FPLINE
FPSHIFT
FPDAT[15:0]
DRDY
t1
t2
Active
Active
T
RESET#
(REG[0Dh] bit 0)
Active
Inactive