Epson S1D13504 ユーザーズマニュアル

Epson Research and Development

Page 65

Vancouver Design Center

Hardware Functional Specification

S1D13504

Issue Date: 01/01/30

X19A-A-002-18

7.4.3 Single Monochrome 4-Bit Panel Timing

Figure 7-19: Single Monochrome 4-Bit Panel Timing

VDP =

Vertical Display Period

= (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1

VNDP =

Vertical Non-Display Period

= (REG[0Ah] bits [5:0]) + 1

HDP =

Horizontal Display Period

= ((REG[04h] bits [6:0]) + 1)*8Ts

HNDP =

Horizontal Non-Display Period

= ((REG[05h] bits [4:0]) + 1)*8Ts

VDP

FPLINE

FPSHIFT

LINE1

LINE2

LINE3

LINE4

LINE239 LINE240

FPFRAME

LINE1

LINE2

FPLINE

MOD

1-2

1-6

1-318

1-3

1-7

1-319

1-4

1-8

1-320

1-1

1-5

1-317

MOD

VNDP

HDP

HNDP

* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 320x240 panel

UD[3:0], UD[3:0]

UD2

UD1

UD0

UD3