Intel 820E ユーザーズマニュアル

Intel

820E Chipset

Design

Guide

Figure 100. 4.5 mil Stack-Up ..................................................................................................181

Figure 101. Intel

820E Chipset Power Delivery Example......................................................184

Figure 102. 1.8 V and 2.5 V Power Sequencing (Schottky Diode) .........................................187

Figure 103. Example 1.8V/3.3V Power Sequencing Circuit ...................................................189

Figure 104. Example 3.3V/5V REF Sequencing Circuitry ......................................................190

Figure 105. Use a GPO to Reduce DRCG Frequency...........................................................191

Figure 106. Example of ICH2 Power Plane Split....................................................................192

Tables

Table 1. Intel

820E Chipset Platform Bandwidth Summary ....................................................17

Table 2. AGP 2× Data/Strobe Association ...............................................................................33

Table 3. Placement Guidelines for Motherboard Routing Lengths...........................................35

Table 4. Copper Tab Area Calculation .....................................................................................42

Table 5. RSL and Clocking Signal RIMM Connector Capacitance Recommendations ...........47

Table 6. Copper Tab Area Calculation .....................................................................................48

Table 7. RSL Routing Layer Requirements..............................................................................50

Table 8. Line Matching and Via Compensation Example.........................................................53

Table 9. Signal List ...................................................................................................................57

Table 10. AGP 2.0 Data/Strobe Associations...........................................................................62

Table 11. AGP 2.0 Routing Summary ......................................................................................64

Table 12. TYPDET#/V

DDQ

Relationship ....................................................................................67

Table 13. Connector / Add-in Card Interoperability ..................................................................71

Table 14. Voltage / Data Rate Interoperability..........................................................................71

Table 15. 8-Bit Hub Interface Buffer Configuration Setting ......................................................75

Table 16. 8-Bit Hub Interface HUBREF Generation Circuit Specifications ..............................76

Table 17. 8-Bit Hub Interface RCOMP Resistor Values ...........................................................77

Table 18.

Signal Descriptions...................................................................................................89

Table 19. Codec Configurations ...............................................................................................90

Table 20. Pull-Up Requirements for SMBus and SMLink Signals............................................95

Table 21. Usage of I/O APIC Interrupt Inputs 16 through 23..................................................101

Table 22. LAN Design Guide Section Reference ...................................................................103

Table 23. Length Requirements for Figure 66........................................................................105

Table 24. Related Documents ................................................................................................112

Table 25. Decoupling Capacitor Recommendation................................................................122

Table 26. PCI Interface...........................................................................................................125

Table 27. Hub Interface ..........................................................................................................126

Table 28. LAN Interface..........................................................................................................126

Table 29. EEPROM Interface .................................................................................................126

Table 30. FWH Flash BIOS Interface.....................................................................................126

Table 31. Interrupt Interface ...................................................................................................127

Table 32. GPIO.......................................................................................................................128

Table 33. USB Interface .........................................................................................................128

Table 34. Power Management ...............................................................................................129

Table 35. Processor Signals...................................................................................................129

Table 36. System Management..............................................................................................130

Table 37. RTC ........................................................................................................................130

Table 38. AC’97......................................................................................................................130

Table 39. Miscellaneous Signals ............................................................................................131

Table 40. Power......................................................................................................................131

Table 41. IDE Checklist ..........................................................................................................132

Table 42. ISA Bridge Checklist...............................................................................................133

Table 43. 8-Bit Hub Interface..................................................................................................134

Table 44. IDE Interface...........................................................................................................134