Renesas R5S72623 ユーザーズマニュアル

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Section 15   Serial Communication Interface with FIFO 
 
 
Page 762 of 2108 
 
R01UH0134EJ0400  Rev. 4.00 
 
 Sep 
24, 
2014 
SH7262 Group, SH7264 Group
(1)  Transmit/Receive Formats 
The data length is fixed at eight bits. No parity bit can be added. 
(2)  Clock 
An internal clock generated by the on-chip baud rate generator by the setting of the C/A bit in 
SCSMR and CKE[1:0] in SCSCR, or an external clock input from the SCK pin can be selected as 
the transmit/receive clock. 
When this module operates on an internal clock, it outputs the clock signal at the SCK pin. Eight 
clock pulses are output per transmitted or received character. When transmission or reception is 
not performed, the clock signal remains in the high state. When only receiving, the clock signal 
outputs while the RE bit of SCSCR is 1 and the number of data in receive FIFO is more than the 
receive FIFO data trigger number. 
(3)  Transmitting and Receiving Data 
  Initialization (Clock Synchronous Mode) 
Before transmitting, receiving, or changing the mode or communication format, the software 
must clear the TE and RE bits to 0 in the serial control register (SCSCR), then initialize this 
module. Clearing TE to 0 initializes the transmit shift register (SCTSR). Clearing RE to 0, 
however, does not initialize the RDF, PER, FER, and ORER flags and receive data register 
(SCRDR), which retain their previous contents.