Renesas R5S72622 ユーザーズマニュアル

 

Section 25   NAND Flash Memory Controller 

R01UH0134EJ0400  Rev. 4.00  

 

Page 1307 of 2108 

Sep 24, 2014 

 

 

 
SH7262 Group, SH7264 Group 

23, 22 

 All 

0 

R 

Reserved 

These bits are always read as 0. The write value 
should always be 0. 

21, 20 

FIFOTRG
[1:0] 

00 R/W 

FIFO Trigger Setting 

Specify the condition (the byte number) for generation 
of FLDTFIFO and FLECFIFO transfer requests. 

  In flash-memory read 

Issue an interrupt to the CPU or issue a DMA 
transfer request when FLDTFIFO (FLECFIFO) 
stores the following number of bytes or more: 

00: 4 (4) 

01: 16 (16) 

10: 128 (4) 

11: 128 (16) 

  In flash-memory programming 

Issue an interrupt to the CPU or issue a DMA 
transfer request when FLDTFIFO (FLECFIFO) has 
the following empty area of bytes or more: 

00: 4 (4) 

01: 16 (16) 

10: 128 (4) 

11: 128 (16) 

Note: For DMA transfer from/to FLDTFIFO, setting 10 

and 11 are prohibited. 

19 AC1CLR 

0 

R/W 

FLECFIFO 

Clear 

Clears FLECFIFO. 

0: Retains the FLECFIFO value. In flash-memory 

access, this bit should be cleared to 0. 

1: Clears FLECFIFO. After FLECFIFO has been 

cleared, this bit should be cleared to 0. 

18 AC0CLR 

0 

R/W 

FLDTFIFO 

Clear 

Clears FLDTFIFO. 

0: Retains the FLDTFIFO value. In flash-memory 

access, this bit should be cleared to 0. 

1: Clears FLDTFIFO. After FLDTFIFO has been 

cleared, this bit should be cleared to 0.