Renesas R5S72621 ユーザーズマニュアル
Section 25 NAND Flash Memory Controller
R01UH0134EJ0400 Rev. 4.00
Page 1311 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit
Name
Initial
Value R/W
Value R/W
Description
1
TRINTE1
0
R/W
FLECFIFO Transfer Request Enable to CPU
Enables or disables an interrupt request to the CPU by
a transfer request issued from FLECFIFO.
a transfer request issued from FLECFIFO.
0: Disables an interrupt request to the CPU by a
transfer request from FLECFIFO.
1: Enables an interrupt request to the CPU by a
transfer request from FLECFIFO.
When the DMA transfer is enabled, this bit should be
cleared to 0.
cleared to 0.
0
TRINTE0
0
R/W
FLDTFIFO Transfer Request Enable to CPU
Enables or disables an interrupt request to the CPU by
a transfer request issued from FLDTFIFO.
a transfer request issued from FLDTFIFO.
0: Disables an interrupt request to the CPU by a
transfer request from FLDTFIFO
1: Enables an interrupt request to the CPU by a
transfer request from FLDTFIFO
When the DMA transfer is enabled, this bit should be
cleared to 0.
cleared to 0.
Note: * Only 0 can be written to these bits.
25.3.9
Ready Busy Timeout Setting Register (FLBSYTMR)
FLBSYTMR is a 32-bit readable/writable register that specifies the timeout time when the FRB
pin is busy.
pin is busy.
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
-
-
-
-
-
-
-
-
-
-
-
RBTMOUT[19:16]
RBTMOUT[15:0]