Intel D425 AU80610006252AA ユーザーズマニュアル
製品コード
AU80610006252AA
Processor Configuration Registers
Datasheet
61
1.5.36
ERRSTS - Error Status
B/D/F/Type: 0/0/0/PCI
Address Offset:
C8-C9h
Default Value:
0000h
Access:
RO; RWC/S;
Size: 16
bits
This register is used to report various error conditions via the SERR DMI messaging
mechanism. An SERR DMI message is generated on a zero to one transition of any of
these flags (if enabled by the ERRCMD and PCICMD registers).
mechanism. An SERR DMI message is generated on a zero to one transition of any of
these flags (if enabled by the ERRCMD and PCICMD registers).
These bits are set regardless of whether or not the SERR is enabled and generated.
After the error processing is complete, the error logging mechanism can be unlocked
After the error processing is complete, the error logging mechanism can be unlocked
by clearing the appropriate status bit by software writing a '1' to it.
Bit Access Default
Value
RST/
PWR
Description
15:13 RO 000b Core
Reserved ()
12 RWC/S 0b Core
GMCH Software Generated Event for SMI
(GSGESMI):
This indicates the source of the SMI was a
Device 2 Software Event.
(GSGESMI):
This indicates the source of the SMI was a
Device 2 Software Event.
11 RWC/S 0b Core
GMCH Thermal Sensor Event for
SMI/SCI/SERR (GTSE):
Indicates that a CPU Uncore Thermal Sensor
trip has occurred and an SMI, SCI or SERR has
been generated. The status bit is set only if a
message is sent based on Thermal event
enables in Error command, SMI command and
SCI command registers. A trip point can
generate one of SMI, SCI, or SERR interrupts
(two or more per event is illegal). Multiple trip
points can generate the same interrupt, if
software chooses this mode, subsequent trips
may be lost. If this bit is already set, then an
interrupt message will not be sent on a new
thermal sensor event.
SMI/SCI/SERR (GTSE):
Indicates that a CPU Uncore Thermal Sensor
trip has occurred and an SMI, SCI or SERR has
been generated. The status bit is set only if a
message is sent based on Thermal event
enables in Error command, SMI command and
SCI command registers. A trip point can
generate one of SMI, SCI, or SERR interrupts
(two or more per event is illegal). Multiple trip
points can generate the same interrupt, if
software chooses this mode, subsequent trips
may be lost. If this bit is already set, then an
interrupt message will not be sent on a new
thermal sensor event.
10 RO 0b Core
Reserved (
9 RWC/S 0b Core
LOCK to non-DRAM Memory Flag (LCKF):
When this bit is set to 1, the CPU Uncore has
detected a lock operation to memory space that
did not map into DRAM.
When this bit is set to 1, the CPU Uncore has
detected a lock operation to memory space that
did not map into DRAM.
8 RO 0b Core
Received Refresh Timeout Flag (RRTOF):
Reserved
Reserved
7 RWC/S 0b Core
DRAM Throttle Flag (DTF):
1: Indicates that a DRAM Throttling condition
occurred.
0: Software has cleared this flag since the
most recent throttling event.
1: Indicates that a DRAM Throttling condition
occurred.
0: Software has cleared this flag since the
most recent throttling event.