Freescale Semiconductor MPC5200B ユーザーズマニュアル

Freescale Semiconductor

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The following sections are contained in this document:

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MPC5200B has three primary reset pins, which are implemented as open drain I/Os

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Power-On Reset—PORRESET

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Hard Reset—HRESET

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Soft Reset—SRESET

PORRESET is a power-on reset input. It is asserted by an external source and must be held active for a specified period of time until power 
is stable to the MPC5200B.

HRESET and SRESET can be asserted by an external source or they can be asserted by reset generation logic internal to MPC5200B.

Internal reset logic analyzes all internal and external reset sources and asserts internal and external reset signals appropriately.

When a hard reset (HRESET) is detected, reset logic counters hold internal and external HRESET for a minimum of 4096 reference clock 
cycles or until the external HRESET source is released, whichever is longer.

PORRESET must be asserted externally when power is applied to the system for a required period of time (see 

When PORRESET is asserted, internal logic forces HRESET and SRESET active. PORRESET must remain asserted until the MPC5200B 
system oscillator begins oscillation and the system APLL establishes a locked condition. 

During PORRESET or HRESET the reset configuration word is sampled to establish the initial state of various vital internal MPC5200B 
functions. The reset configuration word is latched internally when HRESET is released.

When initiated by PORRESET, HRESET asserts and remains asserted for 4096 reference clocks after PORRESET is released.

Source of power-on reset is an external, board level reset source like a push button, reset control logic, etc.

HRESET is a bidirectional signal with a Schmitt-trigger input and an open drain output. HRESET requires an external pull-up. Assertion of 
external HRESET causes external HRESET and SRESET, and internal hard and soft resets, to be asserted for at least 4096 reference clock 
cycles.

During PORRESET or HRESET the reset configuration word is sampled to establish the initial state of various vital internal MPC5200B 
functions. The reset configuration word is latched internally when PORRESET or HRESET is released.

HRESET can also be asserted by internal sources. When HRESET is asserted internally, external HRESET and SRESET are also asserted.

Sources of hard reset are:

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PORRESET or HRESET pins asserted

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Hard reset asserted by debug module

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Reset signal asserted by watchdog timer or checkstop reset

1. All “open drain” outputs of MPC5200B are actually regular 3-state output drivers with the output data tied low, and the output enable controlled. Thus, 

unlike a true open drain, there is a current path from the external system to the MPC5200B I/O power rail if the external signal is driven above the 
MPC5200B I/O power rail voltage.