Freescale Semiconductor MPC5200B ユーザーズマニュアル

Freescale Semiconductor

5-9

Power Management modes are listed below. Details are given in the sections that follow.

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The MPC5200B design is equipped with many power conservation features, which are supported in the peripherals and system logic. The 
e300 Core has its own power-down modes:

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nap

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doze

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sleep

Individual peripheral functions can be disabled by stopping the module’s clock. In addition to clock control of individual peripheral functions, 
clock control sequencer (CCS) logic sequences the MPC5200B clock system to enter and exit a deep-sleep power mode. This limits power 
consumption to device leakage levels.

The MPC5200B system is driven by:

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a 27/33MHz system OSC, and

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a 32KHz real-time clock (RTC) OSC.

The 27/33MHz OSC drives the main clock system through a PLL that multiplies the frequency for the system buses and peripherals on the 
chip. The e300 Core uses the XLB frequency as an input to the microprocessor PLL that generates the internal core frequencies.

The RTC clock domain is completely separate from the 27/33MHz clock domain. All interactions between the RTC clock domain and any 
other are handled with synchronizers.

In Full-Power mode both the system PLL and microprocessor PLL are locked and the main system clocks are supplied to the MPC5200B 
system. In this mode, the e300 Core may use the Dynamic Power Mode (DPM). If this mode is enabled, logic not required for instruction 
execution, is not activated. This results in power reduction over a design that would be fully clocked during normal operation.

Performance in not decreased in Dynamic Power Mode, so it is recommended that it should never be disabled (although it is possible) when 
running the core at full speed.

MPC5200B peripherals can be individually enabled based on what functionality is required by the application running and the external 
stimulus presented to MPC5200B. Peripherals not required can be powered-down through a write to an MPC5200B system control register 
which disables the peripheral and gates the peripheral clock.

Sleep modes in the MPC5200B design can be exercised through microprocessor sleep mode control and peripheral clock disables. In all modes 
except Deep-Sleep mode, the system crystal oscillator is enabled, and the system PLL and microprocessor PLL remain locked. Response time 
to WakeUP interrupts is faster than in the deep-sleep mode (see 

). Since clocks are still running in the 

MPC5200B chip, any interrupt normally present in the MPC5200B design can be used to wake up the power-down logic. See 

, Clock Enable register.

The e300 Core power management modes are listed below. Details are given in the sections that follow.

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 (default power state)

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These modes are controlled by writes to an internal e300 Core control register. These modes only apply to the e300 Core. Logic outside the 
e300 Core remains active unless separately disabled. In any of these modes, peripherals can be enabled or disabled by writing to an 
MPC5200B system control register.