Freescale Semiconductor MPC5200B ユーザーズマニュアル
General Purpose I/O (GPIO)
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
7-25
7.3.1
GPIO Pin Multiplexing
shows the GPIO/Generic MUX cell.
Figure 7-3. GPIO/Generic MUX Cell
Pin MUX Logic
I/O Cell
Alternate Func 1
IN
OUT
BC
Enabled
Alternate Func 2
IN
OUT
BC
Enabled
TIMER
IN
OUT
BC
Enabled
GPIO/d/W
IN
OUT
BC
Enabled
ODconfig
Multi-
Function
Output Enable
Interrupt for WakeUp supported GPIO pins only
Awake
Note:
1.
Open-Drain Emulation is supported on the GPIO function.
2.
Pin MUX Logic is controlled by the Port Configuration Register and supersedes any individual
GPIO register programming.
GPIO register programming.
I/O
Priority
Logic