Freescale Semiconductor MPC5200B ユーザーズマニュアル
MPC5200B Users Guide, Rev. 1
7-50
Freescale Semiconductor
General Purpose I/O (GPIO)
7.3.2.2.5
GPW WakeUp GPIO Interrupt Enable Register—MBAR + 0x0C10
7.3.2.2.6
GPW WakeUp GPIO Individual Interrupt Enable Register —MBAR + 0x0C14
Table 7-41. GPW WakeUp GPIO Interrupt Enable Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
WUPe
Reserved
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Name
Description
0:7
WUPe
Individual bits to enable generation of WakeUp interrupt for WakeUp GPIO configured as
input.
input.
Bit 0 controls GPIO_WKUP_7 (GPIO_WKUP_7 pin)
Bit 1 controls GPIO_WKUP_6 (GPIO_WKUP_6 pin)
Bit 2 controls GPIO_WKUP_5 (PSC6_1 pin)
Bit 3 controls GPIO_WKUP_4 (PSC6_0 pin)
Bit 4 controls GPIO_WKUP_3 (ETH_17 pin)
Bit 5 controls GPIO_WKUP_2 (PSC3_9 pin)
Bit 6 controls GPIO_WKUP_1 (PSC2_4 pin)
Bit 7 controls GPIO_WKUP_0 (PSC1_4 pin)
0 = Pin cannot generate WakeUp Interrupt (default).
1 = Pin can generate WakeUp Interrupt while MPC5200B is in Deep Sleep mode.
Note: These enable bits apply ONLY when MPC5200B is in Deep Sleep mode.
8:31
—
Reserved
Note: Only valid when Port Configuration indicates GPIO usage and pin is configured as input in the associated DDR
bit in GPIOWDO. Also, Master Interrupt Enable bit in GPIOWME must be set.
bit in GPIOWDO. Also, Master Interrupt Enable bit in GPIOWME must be set.
Table 7-42. GPW WakeUp GPIO Individual Interrupt Enable Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
WINe
Reserved
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0