Freescale Semiconductor MPC5200B ユーザーズマニュアル
MPC5200B Users Guide, Rev. 1
7-52
Freescale Semiconductor
General Purpose I/O (GPIO)
7.3.2.2.8
GPW WakeUp GPIO Master Enables Register —MBAR + 0x0C1C
Bit
Name
Description
0:1
Ityp7
GPIO Interrupt Type bits for WakeUp GPIO pins 7–0
00=Interrupt at any transition
01=Interrupt on rising edge
10=Interrupt on falling edge
11=Interrupt on pulse (any 2 transitions)
The above interrupt types describe operation for interrupts occuring while MPC5200B is
not in Deep Sleep mode (i.e., Simple Interrupt types). For operation while in Deep Sleep
mode the interpretation of these bits is slightly different, because no clocking is present in
this mode and it is therefore impossible to detect an edge on the input. For Deep Sleep
mode the bits are interpretted as follows:
not in Deep Sleep mode (i.e., Simple Interrupt types). For operation while in Deep Sleep
mode the interpretation of these bits is slightly different, because no clocking is present in
this mode and it is therefore impossible to detect an edge on the input. For Deep Sleep
mode the bits are interpretted as follows:
00 = Not Valid, no interrupt can be detected
01 = Level High, any high creates WakeUp from Deep Sleep
10 = Level Low, any low creates WakeUp from Deep Sleep
11 = Not Valid, no interrupt can be detected.
ITYP7 controls GPIO_WKUP_7 (GPIO_WKUP_7 pin)
ITYP6 controls GPIO_WKUP_6 (GPIO_WKUP_6 pin)
ITYP5 controls GPIO_WKUP_5 (PSC6_1 pin)
ITYP4 controls GPIO_WKUP_4 (PSC6_0 pin)
ITYP3 controls GPIO_WKUP_3 (ETH_17 pin)
ITYP2 controls GPIO_WKUP_2 (PSC3_9 pin)
ITYP1 controls GPIO_WKUP_1 (PSC2_4 pin)
ITYP0 controls GPIO_WKUP_0 (PSC1_4 pin)
Note: Any GPIO WakeUp interrupt creates a Main Level 2 interrupt in the Interrupt
Controller.
Controller.
2:3
Ityp6
4:5
Ityp5
6:7
Ityp4
8:9
Ityp3
10:11
Ityp2
12:13
Ityp1
14:15
Ityp0
16:31
—
Reserved
Table 7-44. GPW WakeUp GPIO Master Enables Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
ME
Reserved
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0