Freescale Semiconductor MPC5200B ユーザーズマニュアル
DMA (BestComm) Interface (SCLPC)
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
9-11
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BootSwap
describes possible boot settings.
9.6
DMA (BestComm) Interface (SCLPC)
The SCLPC interface provides a separate path from BestComm directly (on CommBus) to any peripheral. The supported transactions are
limited to 1, 2, 4, or 8 bytes only.
limited to 1, 2, 4, or 8 bytes only.
A single FIFO with a size of 512 bytes (32 x 128 bits) supports half duplex operation (Transmit or Receive) only. If software configures a
Transmit Packet, the Packet must be complete before a Receive operation can be configured and started.
Transmit Packet, the Packet must be complete before a Receive operation can be configured and started.
9.7
Programmer’s Model
through
describe in detail the registers and bit meanings for configuring CS operation. There are eight identical chip
select configuration registers, one for each CS output. However, the CS Boot ROM Configuration Register has active defaults for use by
BOOTROM on CS0. All other configuration registers power-up disabled and require software intervention before the corresponding CS
operates. The Chip Select Control Register is the enable register and the Chip Select Status Register serves as a status register. For Burst Mode
the Chip Select Burst Control Register exists and the configuration of Dead cycles are done by the Chip Select Deadcycle Control Register.
BOOTROM on CS0. All other configuration registers power-up disabled and require software intervention before the corresponding CS
operates. The Chip Select Control Register is the enable register and the Chip Select Status Register serves as a status register. For Burst Mode
the Chip Select Burst Control Register exists and the configuration of Dead cycles are done by the Chip Select Deadcycle Control Register.
NOTE
The address range registers for each CS reside in the MMAP register set rather than in the LPC
register set. See
register set. See
9.7.1
Chip Select/LPC Registers—MBAR + 0x0300
There are 12 32-bit Chip Select/LocalPlus (CS/LP) registers. These registers are located at an offset from MBAR of 0x0300. Register
addresses are relative to this offset. Therefore, the actual register address is:
addresses are relative to this offset. Therefore, the actual register address is:
MBAR + 0x0300 + register address
The following registers are available:
Table 9-6. BOOT_CONFIG (RST_CONFIG) Options
Parameter
If Pulled Down (0)
If Pulled Up (1)
Notes
BootType
non-MUXed boot mode
MUXed boot mode
BootSize
non-MUXed type:
8-bit data
24-bit address
non-MUXed type:
16-bit data
16-bit address
MUXed type:
16-bit data
(25 bit address)
(25 bit address)
MUXed type:
32-bit data
(25 bit address)
(25 bit address)
BootMostGr
aphics
-
MostGraphics boot mode.
LargeFlash
-
Large Flash boot mode
when active BootSize defines data
size (8/16)
size (8/16)
BootWait
Minimum Wait states
4 pci_clk cycles
Maximum Wait states:
48 pci_clk cycles
The ACK input can shorten wait
states, if BootDevice supports it.
states, if BootDevice supports it.
BootSwap
no Endian swapping applied to
read from Boot Device
read from Boot Device
Standard Endian swapping
performed on reads from Boot
Device
performed on reads from Boot
Device
If swap indicated:
8-bit access = no swap
16-bit access = 2Byte swap
32-bit access = 4Byte swap
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