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Freescale Semiconductor MPC5200B ユーザーズマニュアル

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MPC5200B Users Guide, Rev. 1
12-16
Freescale Semiconductor
Host Control (HC) Operational Registers
 
12.4.4
Frame Counter Partition—MBAR + 0x1034
This HC partition uses 5 32-bit registers. These registers are located at an offset from MBAR of 0x1034. Register addresses are relative to 
this offset. Therefore, the actual register address is: 
MBAR + 0x1034 + register address
The following registers are available:
•
•
 (0x1038)
•
 (0x103C)
•
 (0x1040)
•
 (0x1044)
12.4.4.1
USB HC Frame Interval Register—MBAR + 0x1034
The HC Frame Interval register contains a 14-bit value that indicates:
•
the bit-time interval in a Frame. For example, between two consecutive SOFs.
•
a 15-bit value that indicates the full speed maximum packet size the HC may transmit or receive without causing scheduling 
overruns.
HCD may carry out minor adjustment on the frame interval by writing a new value over the present one at each SOF. This provides the 
programmability necessary for the HC to synchronize with an external clocking resource and to adjust any unknown local clock offset.
 
Table 12-13. USB HC Done Head Register
msb  0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
DH
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
DH
Reserved
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
0:27
DH
DoneHead—When a TD is complete, HC writes the HcDoneHead content to the TD NextTD 
field. HC then overwrites the HcDoneHead content with the TD address. This is set to 0 when 
HC writes the register content to HCCA. HcInterruptStatus WritebackDoneHead is also set.
28:31
—
Reserved
Table 12-14. USB HC Frame Interval Register
msb  0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
FIT
FSMPS
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
FI
W
RESET:
0
0
1
0
1
1
1
0
1
1
0
1
1
1
1
1