Freescale Semiconductor MPC5200B ユーザーズマニュアル

Freescale Semiconductor

14-29

The RFIFO_CONTROL and TFIFO_CONTROL registers provide programmability of many FIFO behaviors, from last transfer granularity 
to frame operation. Last transfer granularity allows the user to control when the FIFO controller stops requesting data transfers through the 
FIFO alarm. When the alarm is configured as a Receive FIFO, the granularity value is the GR[2:0] value. When the alarm is configured as a 
Transmit FIFO, the granularity value is four times the GR[2:0] value, or the pipeline depth. The frame bit of the control register provides a 
capability to enable and control the FIFO controller’s ability to view data on a packetized basis. The FIFO controller also has the 
programmable capability to not request attention after it has received a complete frame until Ethernet has reported completion of transmission. 
Frame mode supersedes the FIFO granularity bits, through the assertion of a hardware signal to BestComm.

10

UF

UF FIFO Underflow – Sticky, Write To Clear

This bit signifies the read pointer has surpassed the write pointer. This bit will remain set until 
this bit of the FIFO status register has been written with a 1.

11

OF

OF FIFO Overflow – Sticky, Write To Clear

This bit signifies the write pointer has surpassed the read pointer. This bit will remain set until 
this bit of the FIFO status register has been written with a 1.

12

FR

FR Frame Ready – Read Only

The FIFO has requested attention because there is framed data ready. All complete frames 
must be read from the FIFO to clear this alarm. This alarm will only be asserted while in 
frame mode.

13

Full

Full Alarm – Read Only

The FIFO has requested attention because it is full. The FIFO must be read to clear this 
alarm.

14

Alarm

FIFO Alarm – Read Only

The FIFO has requested attention because it has determined an alarm condition. The 
specific alarm condition detected is dependent upon the FIFO direction (Transmit or 
Receive); if it is a Transmit FIFO, then the FIFO alarm output pin provides indication of a low 
level, asserting when there is less than alarm bytes of data remaining in the FIFO, and 
deasserting when there are less than 4* granularity free bytes remaining. When the FIFO is 
configured to Receive, the FIFO alarm provides high level indication, asserting when there 
are less than alarm bytes free in the FIFO, and deasserting when there are less than 
granularity bytes of data remaining. This signal can be cleared by reading or writing (as 
appropriate) the FIFO, or manipulating the FIFO pointers.

15

Empty

Empty – Read Only

The FIFO has requested attention because it is empty. The FIFO must be written to clear this 
alarm.

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Reserved