Freescale Semiconductor MPC5200B ユーザーズマニュアル
MPC5200B Users Guide, Rev. 1
14-30
Freescale Semiconductor
FEC Tx FIFO Status Register—MBAR + 0x31A8
14.8.2
FEC Rx FIFO Last Read Frame Pointer Register—MBAR + 0x3190
FEC Tx FIFO Last Read Frame Pointer Register—MBAR + 0x31B0
The RFIFO_LRF_PTR and TFIFO_LRF_PTR are a FIFO-maintained pointer which indicates the location of the start of the most recently
read frame, or the start of the frame currently in transmission. The LRFP updates on FIFO read data accesses to a frame boundary. The LRFP
can be read and written for debug purposes. For the frame retransmit function, the LRFP indicates which point to begin retransmission of the
data frame. The LRFP carries validity information, however, there are no safeguards to prevent retransmitting data which has been
overwritten. When FRAME is not set, then this pointer has no meaning.
read frame, or the start of the frame currently in transmission. The LRFP updates on FIFO read data accesses to a frame boundary. The LRFP
can be read and written for debug purposes. For the frame retransmit function, the LRFP indicates which point to begin retransmission of the
data frame. The LRFP carries validity information, however, there are no safeguards to prevent retransmitting data which has been
overwritten. When FRAME is not set, then this pointer has no meaning.
Table 14-32. FEC Rx FIFO Control Register
FEC Tx FIFO Control Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Shadow
WFR[1:0]
COMP
FR
AME
GR[2:0]
IP
MASK
FAE
MASK
RXW
MASK
UF
MASK
OF
MAS
K
TXW
MAS
MAS
K
Reserved
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
0
—
Reserved
1:2
WFR[1:0]
Write Frame
01 = the FIFO controller assumes the next write to its data port is the next to last write.
10 = the FIFO controller assumes the next write to its data port is status / control
information.
information.
3
COMP
COMP Re-enable Requests on Frame Transmission Completion.
When this bit is set, the FIFO controller will not request attention between receiving the last
data of the frame from the BestComm until the peripheral acknowledges transmission of the
frame.
data of the frame from the BestComm until the peripheral acknowledges transmission of the
frame.
4
FRAME
Frame Mode Enable.
When this bit is set, the FIFO controller monitors frame done information from the peripheral
or BestComm. Setting this bit also enables the other frame control bits in this register, as well
as other frame functions. This bit must be set to use frame functions.
or BestComm. Setting this bit also enables the other frame control bits in this register, as well
as other frame functions. This bit must be set to use frame functions.
5:7
GR[2:0]
Last Transfer Granularity.
These bits define the deassertion point for the “high” service request and also define the
deassertion point for the “low” service request. A “high” service request is deasserted when
there are less than GR[2:0] data bytes remaining in the FIFO. A “low” service request is
deasserted when there are less than (4 * GR[2:0]) free bytes remaining in the FIFO.
deassertion point for the “low” service request. A “high” service request is deasserted when
there are less than GR[2:0] data bytes remaining in the FIFO. A “low” service request is
deasserted when there are less than (4 * GR[2:0]) free bytes remaining in the FIFO.
Table 14-33. FEC Rx FIFO Last Read Frame Pointer Register
FEC Tx FIFO Last Read Frame Pointer Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0