Freescale Semiconductor MPC5200B ユーザーズマニュアル

Initialization Sequence

MPC5200B Users Guide, Rev. 1

Freescale Semiconductor

14-35

14.9.2

User Initialization (Prior to Asserting ETHER_EN)

The user needs to initialize portions of the FEC prior to setting the ETHER_EN bit. The exact values depend on the particular application; the
sequence of writing the registers is not important. Ethernet MAC registers requiring initialization are defined in

Table 14-41

14.9.2.1

Microcontroller Initialization

In the FEC the descriptor control RISC initializes some registers after ETHER_EN is asserted. After the microcontroller initialization
sequence is complete, hardware is ready for operation.

Table 14-42

shows RISC initialization operations common to the FEC.

14.9.3

Frame Control/Status Words

In the FEC transmit frame control words and receive frame status words cross the following the end of frame data. These words are marked
with a type value of 10 and have the following formats.

14.9.3.1

Receive Frame Status Word

Table 14-2

below defines the format for the receive frame status word.

Bits 31-28, 26-25, 19 and 15-11—Reserved

Table 14-41. User Initialization (Before ETHER_EN)

Description

Initialize IMASK

Clear IEVENT (write FFFF_FFFF)

X_WMRK (optional)

IADDR2/IADDR1

GADDR1/GADDR2

PADDR1/PADDR2

OP_PAUSE (only needed for FDX flow control)

R_CNTRL

X_CNTRL

MII_SPEED (optional)

Clear MIB_RAM (locations 200–2FC)

Table 14-42. Microcontroller Initialization (FEC)

Description

Initialize BackOff random number seed

Activate Receiver

Activate Transmit

Table 14-43. Receive Frame Status Word Format

(Last)

FRAME_LENGTH