Freescale Semiconductor MPC5200B ユーザーズマニュアル
XLB Arbiter Registers—MBAR + 0x1F00
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
16-9
16.2.8
Arbiter Data Tenure Time-Out Register (R/W)—MBAR + 0x1F5C
The Arbiter Data Tenure Time-out Register provides an expiration value to the arbiter watchdog for data tenures. After a data tenure is initiated
with a DBB signal assertion by the master, the data tenure watchdog starts counting until either TA is asserted, or the counter expires. If
expiration occurs before TA is encountered, the arbiter issues a TEA assertion for the data tenure. Subsequently, the Arbiter Status Register,
bit 30 (DT) is set, and an interrupt is generated if the Arbiter Interrupt Enable Register, bit 30 (DTE) is set.
with a DBB signal assertion by the master, the data tenure watchdog starts counting until either TA is asserted, or the counter expires. If
expiration occurs before TA is encountered, the arbiter issues a TEA assertion for the data tenure. Subsequently, the Arbiter Status Register,
bit 30 (DT) is set, and an interrupt is generated if the Arbiter Interrupt Enable Register, bit 30 (DTE) is set.
The Arbiter Data Tenure watchdog can be enabled/disabled via the Arbiter Configuration Register, bit 29 (AT).
16.2.9
Arbiter Bus Activity Time-Out Register (R/W)—MBAR + 0x1F60
The Arbiter Bus Activity Time-out Register provides an expiration value to the arbiter watchdog for bus activity. The watchdog monitors bus
activity, after the counter expires due to excessive bus idle time, the Arbiter Status Register, bit 29 (BA) is set, and an interrupt is generated
if the Arbiter Interrupt Enable Register, bit 29 (BAE) is set.
activity, after the counter expires due to excessive bus idle time, the Arbiter Status Register, bit 29 (BA) is set, and an interrupt is generated
if the Arbiter Interrupt Enable Register, bit 29 (BAE) is set.
The Arbiter Bus Activity watchdog can be enabled/disabled via the Arbiter Configuration Register, bit 28 (BA).
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
ADRTO[16:31]
W
RESET:
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bit
Name
Description
0:3
—
Reserved
4:31
ADRTO
Address Tenure Time-out. Contains the upper 28 bits of the Address Time-out Counter.
Values represent increments of 16. Default value is 0xFFFFFFF.
Values represent increments of 16. Default value is 0xFFFFFFF.
Table 16-8. Arbiter Data Tenure Time-Out Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Rsvd
DATTO[4:15]
W
RESET:
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
DATTO[16:31]
W
RESET:
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bit
Name
Description
0:3
—
Reserved
4:31
DATTO
Data Tenure Time-out. Contains the upper 28 bits of the DataTime-out Counter. Values
represent increments of 16. Default value is 0xFFFFFFF.
represent increments of 16. Default value is 0xFFFFFFF.
Table 16-9. Arbiter Bus Activity Time-Out Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
BUSTO[0:15]
W
RESET:
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1