Freescale Semiconductor MPC5200B ユーザーズマニュアル
MPC5200B Users Guide, Rev. 1
16-10
Freescale Semiconductor
XLB Arbiter Registers—MBAR + 0x1F00
16.2.10
Arbiter Master Priority Enable Register (R/W)—MBAR + 0x1F64
The Arbiter Master Priority Enable Register determines whether the arbiter uses the hard-wired or software programmable priority for a
master. The default is enabled for all masters. Both methods may be employed at the same time for different masters. This register may be
written to at any time, and the change becomes effective one clock after the register is written.
master. The default is enabled for all masters. Both methods may be employed at the same time for different masters. This register may be
written to at any time, and the change becomes effective one clock after the register is written.
When enabled, the software programmable value in the Arbiter Master N Priority Register is used as the priority for the master. When
disabled, the priority assignment for each master is determined by the hardware-wired mNpri signals, as shown in
disabled, the priority assignment for each master is determined by the hardware-wired mNpri signals, as shown in
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
BUSTO[16:31]
W
RESET:
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bit
Name
Description
0:31
BUSTO
Bus Activity Time-out. Contains the value of the Bus Activity Time-out Counter. Values
represent increments of 1. Default value is 0xFFFFFFFF.
represent increments of 1. Default value is 0xFFFFFFFF.
Table 16-10. Arbiter Master Priority Enable Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Rsvd
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Rsvd
M7
M6
M5
M4
M3
M2
M1
M0
W
RESET:
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Bit
Name
Description
0:23
—
Reserved
24
M7
Master 7 Priority Register Enable
25
M6
Master 6 Priority Register Enable
26
M5
Master 5 Priority Register Enable
27
M4
Master 4 Priority Register Enable
28
M3
Master 3 Priority Register Enable
29
M2
Master 2 Priority Register Enable
30
M1
Master 1 Priority Register Enable
40
M0
Master 0 Priority Register Enable
Table 16-11. Hardware Assignments of Master Priority
Master
Priority
Description
M7–M4
—
Unused
M3
0
PCI Target Interface