Freescale Semiconductor MPC5200B ユーザーズマニュアル

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Freescale Semiconductor

The I

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C has simple bidirectional two-wire bus for efficient inter-IC control. The two wires, serial data line (SDA) and serial clock line (SCL), 

carry information between MPC5200B and other devices connected to the bus. Each device, including MPC5200B, is recognized by a unique 
address, and can operate as either transmitter or receiver, depending on the function of the device. In addition to the transmitters and receivers, 
devices can be considered as masters or slaves. A master is the device which initiates a data transfer on the bus and generates the clock signals 
to permit that transfer. At that time, any device addressed is considered a slave. See 

.

Standard communication usually has 4 functional areas:

•

START  signal

•

slave address transmission

•

data transfer

•

STOP signal

Activities listed above are briefly described in the sections below. Also see 

.

A START signal is defined as a high-to-low transition of SDA while SCL is high. This signal denotes the beginning of a new data transfer 
and wakes up all slaves. Each data transfer may contain several data bytes.

When the bus is free, (i.e., no master device is engaging the bus) both SCL and SDA lines are at a logical high. A master initiates 
communication by sending a START signal.

A STOP signal is defined as a low-to-high transition of SDA while SCL is high.

Transmitter

Device that sends data to bus.

Receiver

Device that receives data from bus.

Master

Device that initiates transfer, generates SCL, and terminates transfer.

Slave

Device that is addressed by master.

IP Bus

Address

Compare

Data Shift

Register

In/Out

Start, Stop

& Arbitration

Control

Control

Clock

Registers

SCL

SDA

CommBus