Freescale Semiconductor MPC5200B ユーザーズマニュアル

Freescale Semiconductor

19-39

An overrun of the receiver FIFO, error,  warning or Bus-Off condition occurred. The 

 indicates one of the following conditions:

•

Overrun

An overrun condition of the receiver FIFO as described in 

 occurred.

•

CAN Status Change

The actual value of the Transmit and Receive Error Counters control the bus state of the MSCAN. 
As soon as the error counters skip into a critical range (Tx/Rx-Warning, Tx/Rx-Error, Bus-Off) the MSCAN flags an error condition. 
The status change, which caused the error condition, is indicated by the TSTAT and RSTAT flags (see section 

).

Interrupts are directly associated with one or more status flags in either the 

 or the 

Interrupts are pending as long as one of the corresponding flags is set. The flags in the above registers must be reset within the interrupt handler 
to handshake the interrupt. The flags are reset by writing a “1” to the corresponding bit position. A flag cannot be cleared if the respective 
condition still prevails.

It must be guaranteed that the CPU only clears the bit causing the current interrupt. For this reason, 
bit manipulation instructions (BSET) must not be used to clear interrupt flags. These instructions may 
cause accidental clearing of interrupt flags which are set after entering the current interrupt service 
routine.

The MSCAN can recover from Sleep Mode via the Wake-Up interrupt. This interrupt can only occur if the MSCAN is in Sleep Mode 
(SLPRQ=1 and SLPAK=1), the wake-up option is enabled (WUPE=1) and the Wake-Up interrupt is enabled (WUPIE=1).