Freescale Semiconductor MPC5200B ユーザーズマニュアル
TLM Link DR Instructions
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
21-7
Figure 21-5. e300 Core JTAG/COP Serial Interface
21.7
TLM Link DR Instructions
— C A U T I O N —
1.
For the following registers, only the instruction codes listed should be used. All other codes must be considered private and
potentially damaging.
potentially damaging.
2.
“Persistent” means an instruction’s effect(s) persist even after it is overwritten in the register.
3.
The reset value shown is the update register reset value. Per the JTAG standard, the raw IR shift register reset value is irrelevant.
Link pseudo-instructions are loaded into the 2-bit TLM:Link DR when it is selected by instructions of the TLM or slave TAP blocks. The
value shifted into the TLM:Link DR determines which IR will be active after the Update-DR state. The selection remains in effect until the
TLM:Link register is selected again, and modified.
value shifted into the TLM:Link DR determines which IR will be active after the Update-DR state. The selection remains in effect until the
TLM:Link register is selected again, and modified.
Table 21-1. TLM Link-DR Instructions
Instruction
Encoding (ENA[1:0])
Persistent
TLM:TLMENA
01
N
3
TLM:PPCENA
10
N
Note:
1.
Reset = TLM:TLMENA
2.
Capture = Current Value
3.
Link Pseudo-instructions are persistent with respect to the enabled IR, but not with respect to the contents of the
TLM:Link DR itself.
TLM:Link DR itself.
Boundry Scan
External Memory Scan
RunN Counter
COP_PVR
TDI
TDO
Instruction/Status Register
D
Q
TCK
TMS
TRST
TAP Controller
COP Controller
Long Shift Register Latch