Freescale Semiconductor MPC5200B ユーザーズマニュアル
MPC5200B Users Guide, Rev. 1
21-8
Freescale Semiconductor
TLM Test Instructions
21.7.1
TLM:TLMENA
The TLM:TLMENA pseudo-instruction selects the 6-bit TLM IR.
21.7.2
TLM:PPCENA
The TLM:PPCENA pseudo-instruction selects the 8-bit microprocessor CPU test IR.
21.8
TLM Test Instructions
The TLM IR activates device-level functions, including the mandatory JTAG instructions and private device test data registers.
21.8.1
IDCODE
The IDCODE instruction selects the 32-bit DeviceID DR to be logically connected between TDI and TDO during DR shift operations. The
capture value of the DeviceID DR identifies the manufacturer (Freescale), device type (MPC5200B), and device revision level.
capture value of the DeviceID DR identifies the manufacturer (Freescale), device type (MPC5200B), and device revision level.
21.8.1.1
Device ID Register
21.8.2
BYPASS
The BYPASS instruction selects the 1-bit Bypass DR to be logically connected between TDI and TDO during DR shift operations. It performs
no testing function. The Bypass register provides for a minimum-length serial datapath from TDI to TDO. This allows more rapid test data
movement to and from other JTAG scan chain components. The Bypass register capture value is 0. The Bypass register update value has no
effect.
no testing function. The Bypass register provides for a minimum-length serial datapath from TDI to TDO. This allows more rapid test data
movement to and from other JTAG scan chain components. The Bypass register capture value is 0. The Bypass register update value has no
effect.
21.8.3
SAMPLE/PRELOAD
The SAMPLE/PRELOAD instruction selects the Boundary Scan DR to be logically connected between TDI and TDO during DR shift
operations. As the name implies, the SAMPLE/PRELOAD instruction has two distinct uses:
operations. As the name implies, the SAMPLE/PRELOAD instruction has two distinct uses:
Sample: To capture and examine the device pins state without disturbing normal system operation. Signals are captured at the TCK rising
edge in the Capture-DR state, and examined by shifting out. For captured values to be meaningful, TCK may need to be synchronized
to the normal system clock. The update value has no effect.
edge in the Capture-DR state, and examined by shifting out. For captured values to be meaningful, TCK may need to be synchronized
to the normal system clock. The update value has no effect.
Table 21-2. TLM Test Instruction Encoding
Instruction
Encoding
Persistent
TLM Register
IDCODE
011101
N
Device_ID
BYPASS
111111
N
Bypass
SAMPLE/PRELOAD
100000
N
Boundary
EXTEST
000000
N
Boundary
CLAMP
100001
N
Bypass
HIGHZ
011111
N
Bypass
RESET: IDCODE
Capture: IDCODE
Table 21-3. Device ID Register = 1001 101D hex
Version
Device (MPC5200B
– Initial Release)
Manufacturer (Freescale)
0001
0000 0000 0001 0001
0000 0001 110
1
0
1
1
1
1
0