Intel P4500 CP80617004803AA データシート
製品コード
CP80617004803AA
Features Summary
14
Datasheet
Processor core -> DMI
APIC and MSI interrupt messaging support:
Message Signaled Interrupt (MSI and MSI-X) messages
Downstream SMI, SCI and SERR error indication.
Legacy support for ISA regime protocol (PHOLD/PHOLDA) required for parallel port
DMA, floppy drive, and LPC bus masters.
DMA, floppy drive, and LPC bus masters.
DC coupling no capacitors between the processor and the PCH.
Polarity inversion.
PCH end-to-end lane reversal across the link.
Supports Half Swing low-power/low-voltage.
1.3.4
Platform Environment Control Interface (PECI)
The PECI is a one-wire interface that provides a communication channel between a
PECI client (the processor) and a PECI master (the PCH).
PECI client (the processor) and a PECI master (the PCH).
1.3.5
Intel® HD Graphics Controller
The integrated graphics controller contains a refresh of the fifth generation graphics
core
core
Intel® Dynamic Video Memory Technology (Intel® DVMT) support
Intel® Graphics Performance Modulation Technology (Intel® GPMT)
Intel® Smart 2D Display Technology (Intel® S2DDT)
Intel® Clear Video Technology
MPEG2 Hardware Acceleration
WMV9/VC1 Hardware Acceleration
AVC Hardware Acceleration
ProcAmp
Advanced Pixel Adaptive De-interlacing
Sharpness Enhancement
De-noise Filter
High Quality Scaling
Film Mode Detection (3:2 pull-down) and Correction
Intel® TV Wizard
12 EUs
Dedicated analog and digital display ports are supported through the Intel 5 Series
Chipset PCH
Chipset PCH