Intel P4500 CP80617004803AA データシート
製品コード
CP80617004803AA
Datasheet
33
Interfaces
2.4.2.1.3
Cursors A and B
Cursors A and B are small, fixed-sized planes dedicated for mouse cursor acceleration,
and are associated with Planes A and B respectively. These planes support resolutions
up to 256 x 256 each.
and are associated with Planes A and B respectively. These planes support resolutions
up to 256 x 256 each.
2.4.2.1.4
VGA
Used for boot, safe mode, legacy games, etc. Can be changed by an application without
OS/driver notification, due to legacy requirements.
OS/driver notification, due to legacy requirements.
2.4.2.2
Display Pipes
The display pipe blends and synchronizes pixel data received from one or more display
planes and adds the timing of the display output device upon which the image is
displayed. This is clocked by the Display Reference clock inputs.
planes and adds the timing of the display output device upon which the image is
displayed. This is clocked by the Display Reference clock inputs.
The display pipes A and B operate independently of each other at the rate of 1 pixel per
clock. They can attach to any of the display ports. Each pipe sends display data to the
PCH over the Intel Flexible Display Interface (Intel FDI).
clock. They can attach to any of the display ports. Each pipe sends display data to the
PCH over the Intel Flexible Display Interface (Intel FDI).
2.4.2.3
Display Ports
The display ports consist of output logic and pins that transmit the display data to the
associated encoding logic and send the data to the display device (i.e., LVDS, HDMI,
DVI, SDVO, etc.). All display interfaces connecting external displays are now
repartitioned and driven from the PCH with the exception of the eDP DisplayPort.
associated encoding logic and send the data to the display device (i.e., LVDS, HDMI,
DVI, SDVO, etc.). All display interfaces connecting external displays are now
repartitioned and driven from the PCH with the exception of the eDP DisplayPort.
2.4.2.4
Embedded DisplayPort (eDP)
The DisplayPort abbreviated as DP (different than the generic term display port)
specification is a VESA standard. DisplayPort consolidates internal and external
connection methods to reduce device complexity, support cross industry applications,
and provide performance scalability. The integrated graphics supports an embedded
DisplayPort (eDP) interface for display devices that are integrated into the system
(e.g., laptop LCD panel). All other display interfaces connecting to the LVDS or external
panels are driven from the PCH.
specification is a VESA standard. DisplayPort consolidates internal and external
connection methods to reduce device complexity, support cross industry applications,
and provide performance scalability. The integrated graphics supports an embedded
DisplayPort (eDP) interface for display devices that are integrated into the system
(e.g., laptop LCD panel). All other display interfaces connecting to the LVDS or external
panels are driven from the PCH.
The eDP interface is physically shared with a subset of the PCIe interface. Specifically,
eDP[3:0] map to Logical Lanes PEG[12:15] of the PCIe interface. Mapping for reversed
case is: eDP[3:0] maps to PEG[3:0], ex: eDP[0]=PEG[15] in non reversed case. In
reversed case: eDP[0] = PEG[0].
eDP[3:0] map to Logical Lanes PEG[12:15] of the PCIe interface. Mapping for reversed
case is: eDP[3:0] maps to PEG[3:0], ex: eDP[0]=PEG[15] in non reversed case. In
reversed case: eDP[0] = PEG[0].
Table 2-3. eDP/PEG Ball Mapping
eDP Signal
PEG Signal
Lane Reversal
eDP_AUX
PEG_RX[13]
PEG_RX[2]
eDP_AUX#
PEG_RX#[13]
PEG_RX#[2]
eDP_HPD#
PEG_RX[12]
PEG_RX[3]