Intel J1850 FH8065301455200 ユーザーズマニュアル

Intel

製品コード

FH8065301455200

Datasheet

179

Serial ATA (SATA)

13.8

SATA AHCI Memory Mapped IO Registers

Table 103.

Summary of SATA AHCI Memory Mapped I/O Registers—ABAR

Offset

Size

Register ID—Description

Default

Value

0h

4

“HBA Capabilities (GHC_CAP)—Offset 0h” on page 180

DF20FF02h

4h

4

“HBA Capabilities (GHC_CAP)—Offset 0h” on page 180

00000000h

8h

4

“Interrupt Status (IS)—Offset 8h” on page 183

00000000h

Ch

4

“Ports Implemented (GHC_PI)—Offset Ch” on page 183

00000000h

10h

4

“AHCI Version (VS)—Offset 10h” on page 184

00010300h

24h

4

“HBA Capabilities Extended (GHC_CAP2)—Offset 24h” on page 185

0000003Ch

A0h

4

“Vendor Specific (VSP)—Offset A0h” on page 186

00000048h

A4h

4

“Vendor Specific Capabilities (VS_CAP)—Offset A4h” on page 187

018002FEh

C4h

2

“Premium Feature Block (PFB)—Offset C4h” on page 188

0000h

C8h

2

“SW Feature Mask (SFM)—Offset C8h” on page 189

003Fh

100h

4

“Port-Command List Base Address (PxCLB0)—Offset 100h” on page 190

00000000h

104h

4

“Port-Command List Base Address Upper 32-bits (PxCLBU0)—Offset 104h” on

00000000h

108h

4

“Port-FIS Base Address (PxFB0)—Offset 108h” on page 191

00000000h

10Ch

4

“Port-FIS Base Address Upper 32-bits (PxFBU0)—Offset 10Ch” on page 191

00000000h

110h

4

“Port-Interrupt Status (PxIS0)—Offset 110h” on page 192

00000000h

114h

4

“Port-Interrupt Enable (PxIE0)—Offset 114h” on page 193

00000000h

118h

4

“Port-Command (PxCMD0)—Offset 118h” on page 195

00000004h

120h

4

“Port-Task File Data (PxTFD0)—Offset 120h” on page 197

0000007Fh

124h

4

“Port-Signature (PxSIG0)—Offset 124h” on page 198

FFFFFFFFh

128h

4

“Port-Serial ATA Status (PxSSTS0)—Offset 128h” on page 198

00000000h

12Ch

4

“Port-Serial ATA Control (PxSCTL0)—Offset 12Ch” on page 199

00000000h

130h

4

“Port-Serial ATA Error (PxSERR0)—Offset 130h” on page 200

00000000h

134h

4

“Port-Serial ATA Active (PxSACT0)—Offset 134h” on page 201

00000000h

138h

4

“Port-Commands Issued (PxCI0)—Offset 138h” on page 201

00000000h

144h

4

“Port-Device Sleep (PxDEVSLP0)—Offset 144h” on page 202

1E022852h

180h

4

“Port-Command List Base Address (PxCLB1)—Offset 180h” on page 203

00000000h

184h

4

“Port-Command List Base Address Upper 32-bits (PxCLBU1)—Offset 184h” on

00000000h

188h

4

“Port-FIS Base Address (PxFB1)—Offset 188h” on page 204

00000000h

18Ch

4

“Port-FIS Base Address Upper 32-bits (PxFBU1)—Offset 18Ch” on page 204

00000000h

190h

4

“Port-Interrupt Status (PxIS1)—Offset 190h” on page 205

00000000h

194h

4

“Port-Interrupt Enable (PxIE1)—Offset 194h” on page 206

00000000h

198h

4

“Port-Command (PxCMD1)—Offset 198h” on page 208

00000004h

1A0h

4

“Port-Task File Data (PxTFD1)—Offset 1A0h” on page 211

0000007Fh

1A4h

4

“Port-Signature (PxSIG1)—Offset 1A4h” on page 212

FFFFFFFFh

1A8h

4

“Port-Serial ATA Status (PxSSTS1)—Offset 1A8h” on page 212

00000000h

1ACh

4

“Port-Serial ATA Control (PxSCTL1)—Offset 1ACh” on page 213

00000000h

1B0h

4

“Port-Serial ATA Error (PxSERR1)—Offset 1B0h” on page 214

00000000h

1B4h

4

“Port-Serial ATA Active (PxSACT1)—Offset 1B4h” on page 215

00000000h