Intel J1850 FH8065301455200 ユーザーズマニュアル

180

Datasheet

This register indicates basic capabilities of the HBA to driver software. The RWO bits in 

this register are only cleared upon Backbone Reset.

Default: DF20FF02h

1B8h

4

00000000h

1C4h

4

1E022852h

580h

4

00000000h

584h

4

00000000h

Type: Memory Mapped I/O Register

(Size: 32 bits)

ABAR Type: PCI Configuration Register (Size: 32 bits)
ABAR Reference: [B:0, D:19, F:0] + 24h

31

28

24

20

16

12

8

4

0

1 1 0 1 1 1 1 1 0 0 1 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 0

S64A

SC

QA

SS

N

T

F

SMP

S

SSS

SA

LP

SA

L

SC

LO

IS

S

SNZ

O

SA

M

SMP

FBS

S

PMD

SS

C

PS

C

NCS

C

CCS

EM

S

SX

S

NP

31

1h

RW/O

Supports 64-bit Addressing (S64A): Indicates the S-ATA controller can access 64-bit 

data structures. The 32-bit upper bits of the port DMA Descriptor, the PRD Base, and 

each PRD entry are read/write.

30

1h

RW/O

Supports Native Command Queuing Acceleration (SCQA): Indicates the SATA 

controller supports Serial-ATA Native Command Queuing. The HBA will handle DMA 

Setup FISes in hardware, including support for auto-activate optimization through the 

FIS.

29

0h

RO

Supports SNotification Register (SSNTF): When set to 1, indicates that the HBA 

supports the PxSNTF (SNotification) register and its associated functionality. When 

cleared to 0, the HBA does not support the PxSNTF (SNotification) register and its 

associated functionality.

28

1h

RW/O

Supports Mechanical Presence Switch (SMPS): When set to 1, the HBA supports 

mechanical presence switches on its ports for use in hot plug operations. When cleared 

to 0, this function is not supported. This value is loaded by the BIOS prior to OS 

initialization.

27

1h

RW/O

Supports Staggered Spin-up (SSS): Indicates whether the S-ATA controller supports 

staggered spin-up on its ports, for use in balancing power spikes. This value is loaded by 

platform BIOS prior to OS initialization.

26

1h

RW/O

Supports Aggressive Link Power Management (SALP): Indicates the S-ATA 

controller supports auto-generating link requests to the partial or slumber states when 

there are no commands to process. When cleared to 0, software shall treat the 

PxCMD.ALPE and PxCMD.ASP bits as reserved.

25

1h

RW/O

Supports Activity LED (SAL): Indicates the S-ATA controller supports a single output 

pin (SATALED#) which indicates activity.