Microchip Technology MCU PIC10F322T-I/OT SOT-23-6 MCP PIC10F322T-I/OT データシート

DS41585A-page 62

 2011 Microchip Technology Inc.

; This row erase routine assumes the following:

; 1. A valid address within the erase row is loaded in ADDRH:ADDRL

; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM)

BCF

INTCON,GIE

; Disable ints so required sequences will execute properly

BANKSEL

PMADRL

; not required on devices with 1 Bank of SFRs

MOVF

ADDRL,W

; Load lower 8 bits of erase address boundary

MOVWF

PMADRL

MOVF

ADDRH,W

; Load upper 6 bits of erase address boundary

MOVWF

PMADRH

BCF

PMCON1,CFGS 

; Not configuration space

BSF

PMCON1,FREE

; Specify an erase operation

BSF

PMCON1,WREN 

; Enable writes

MOVLW

55h 

; Start of required sequence to initiate erase

MOVWF

PMCON2 ; 

Write 

55h

MOVLW 0AAh 

;

MOVWF

PMCON2 ; 

Write 

AAh

BSF

PMCON1,WR 

; Set WR bit to begin erase

NOP 

; NOP instructions are forced as processor starts

NOP

; row erase of program memory.

;

; The processor stalls until the erase process is complete

; after erase processor continues with 3rd instruction

BCF

PMCON1,WREN

; Disable writes

BSF

INTCON,GIE

; Enable interrupts

Required

Sequen

ce