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Initialization and Configuration
12.4.2 Configuring a Memory-to-Memory Transfer
μDMA channels 0, 18, 19, and 20 are dedicated for software-initiated transfers. This specific example
uses channel 0. No attributes must be set for a software-based transfer. The attributes are cleared by
default, but are explicitly cleared as shown in the following sections.
uses channel 0. No attributes must be set for a software-based transfer. The attributes are cleared by
default, but are explicitly cleared as shown in the following sections.
12.4.2.1 Configure the Channel Attributes
Configure the channel attributes as follows, or use the driver library function
uDMAChannelAttributeDisable(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32Attr).
uDMAChannelAttributeDisable(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32Attr).
1. Program bit 0 of the DMA Set Channel Priority [UDMA_SETCHNLPRIORITY] register or the DMA
Clear Channel Priority [UDMA_ CLEARCHNLPRIORITY] register to set the channel to high priority or
default priority.
default priority.
2. Set bit 0 of the DMA Clear Channel Primary Alternate [UDMA_ CLEARCHNLPRIALT] register to select
the primary channel control structure for this transfer.
3. Set bit 0 of the DMA Channel Clear Useburst [UDMA_ CLEARBURST] register to allow the
μDMA
controller to respond to single requests and burst requests.
4. Set bit 0 of the DMA Clear Channel Request Mask [UDMA_ CLEARREQMASK] register to allow the
μDMA controller to recognize requests for this channel.
12.4.2.2 Configure the Channel Control Structure
This example transfers 256 words from one memory buffer to another. Channel 0 is used for a software
transfer, and the control structure for channel 0 must be configured to transfer 8-bit data with source and
destination increments in bytes and byte-wise buffer copy. A bus arbitration size of eight can be used
here.
transfer, and the control structure for channel 0 must be configured to transfer 8-bit data with source and
destination increments in bytes and byte-wise buffer copy. A bus arbitration size of eight can be used
here.
The transfer buffer and transfer size are now configured. The transfer uses auto mode, which means that
the transfer automatically runs to completion after the first request.
the transfer automatically runs to completion after the first request.
12.4.2.3 Start the Transfer
Finally, the channel must be enabled. A request must also be made because this is a software-initiated
transfer. The request starts the transfer.
transfer. The request starts the transfer.
1. Enable global interrupts (IntMasterEnable();) and enable interrupt for DMA (IntEnable(uint32_t
ui32Interrupt)).
2. Enable the channel by setting bit 0 of the DMA Set Channel Enable Set [UDMA_ SETCHANNELEN]
register.
3. Issue a transfer request by setting bit 0 of the DMA Channel Software Request [UDMA_ SOFTREQ]
register.
4. The
μDMA transfer begins. If the interrupt is enabled, then the processor is notified by interrupt when
the transfer completes.
If needed, the status can be checked by reading bit 0 of the [UDMA_SETCHANNELEN] register. This bit
is automatically cleared when the transfer completes.
is automatically cleared when the transfer completes.
12.4.3 Configuring Channel Assignments
Channel assignments for each
μDMA channel can be changed using the [CHMAPn] registers. Each 4-bit
field represents a
μDMA channel. If the bit is set, then the secondary function is used for the channel.
See
for channel assignments.
12.5 µDMA Registers
1052
Micro Direct Memory Access (µDMA)
SWCU117A – February 2015 – Revised March 2015
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