Texas Instruments CC2650DK マニュアル

目次

• Table of Contents

  2
• Revision History

  10
• Preface

  11
• 1 Architectural Overview

  13
  • 1.1 Target Applications

    14
  • 1.2 Overview

    14
  • 1.3 Functional Overview

    17
    • 1.3.1 ARM Cortex-M3

      17
      • 1.3.1.1 Processor Core

        17
      • 1.3.1.2 System Timer (SysTick)

        18
      • 1.3.1.3 Nested Vector Interrupt Controller

        18
      • 1.3.1.4 System Control Block

        18
    • 1.3.2 On-Chip Memory

      18
      • 1.3.2.1 SRAM

        18
      • 1.3.2.2 Flash Memory

        19
      • 1.3.2.3 ROM

        19
    • 1.3.3 Radio

      19
    • 1.3.4 AES Engine With 128-Bit Key Support

      19
    • 1.3.5 General-Purpose Timers

      20
      • 1.3.5.1 Watchdog Timer

        20
      • 1.3.5.2 Always-on Domain

        20
    • 1.3.6 Direct Memory Access

      20
    • 1.3.7 System Control and Clock

      21
    • 1.3.8 Serial Communications Peripherals

      21
      • 1.3.8.1 UART

        22
      • 1.3.8.2 I2C

        22
      • 1.3.8.3 I2S

        23
      • 1.3.8.4 SSI

        23
    • 1.3.9 Programmable IOs

      24
    • 1.3.10 Sensor Controller

      24
    • 1.3.11 Random Number Generator

      25
    • 1.3.12 cJTAG and JTAG

      25
    • 1.3.13 Power Supply System

      25
      • 1.3.13.1 Supply System

        25
        • 1.3.13.1.1 VDDS

          26
        • 1.3.13.1.2 VDDR

          26
        • 1.3.13.1.3 Digital Core Supply

          27
        • 1.3.13.1.4 Other Internal Supplies

          27
      • 1.3.13.2 DC-DC Converter

        27
      • 1.3.13.3 External Regulator Mode (1.65-V to 1.95-V Supply Voltage)

        27
• 2 The Cortex-M3 Processor

  28
  • 2.1 The Cortex-M3 Processor Introduction

    29
  • 2.2 Block Diagram

    29
  • 2.3 Overview

    30
    • 2.3.1 System-Level Interface

      30
    • 2.3.2 Integrated Configurable Debug

      30
    • 2.3.3 Trace Port Interface Unit

      31
    • 2.3.4 Cortex-M3 System Component Details

      31
  • 2.4 Programming Model

    31
    • 2.4.1 Processor Mode and Privilege Levels for Software Execution

      32
    • 2.4.2 Stacks

      32
    • 2.4.3 Exceptions and Interrupts

      32
    • 2.4.4 Data Types

      32
  • 2.5 Coretex-M3 Core Registers

    33
    • 2.5.1 Core Register Map

      34
    • 2.5.2 Core Register Descriptions

      34
      • 2.5.2.1 Cortex General-Purpose Register 0 (R0)

        34
      • 2.5.2.2 Cortex General-Purpose Register 1 (R1)

        35
      • 2.5.2.3 Cortex General-Purpose Register 2 (R2)

        35
      • 2.5.2.4 Cortex General-Purpose Register 3 (R3)

        35
      • 2.5.2.5 Cortex General-Purpose Register 4 (R4)

        36
      • 2.5.2.6 Cortex General-Purpose Register 5 (R5)

        36
      • 2.5.2.7 Cortex General-Purpose Register 6 (R6)

        36
      • 2.5.2.8 Cortex General-Purpose Register 7 (R7)

        37
      • 2.5.2.9 Cortex General-Purpose Register 8 (R8)

        37
      • 2.5.2.10 Cortex General-Purpose Register 9 (R9)

        37
      • 2.5.2.11 Cortex General-Purpose Register 10 (R10)

        38
      • 2.5.2.12 Cortex General-Purpose Register 11 (R11)

        38
      • 2.5.2.13 Cortex General-Purpose Register 12 (R12)

        38
      • 2.5.2.14 Stack Pointer (SP)

        39
      • 2.5.2.15 Link Register (LR)

        39
      • 2.5.2.16 Program Counter (PC)

        40
      • 2.5.2.17 Program Status Register (PSR)

        40
      • 2.5.2.18 Priority Mask Register (PRIMASK)

        44
      • 2.5.2.19 Fault Mask Register (FAULTMASK)

        45
      • 2.5.2.20 Base Priority Mask Register (BASEPRI)

        46
      • 2.5.2.21 Control Register (CONTROL)

        47
  • 2.6 Instruction Set Summary

    47
  • 2.7 Cortex-M3 Processor Registers

    50
    • 2.7.1 CPU_ITM Registers

      51
      • 2.7.1.1 STIM0 Register (Offset = 0h) [reset = 0h]

        52
      • 2.7.1.2 STIM1 Register (Offset = 4h) [reset = 0h]

        53
      • 2.7.1.3 STIM2 Register (Offset = 8h) [reset = 0h]

        54
      • 2.7.1.4 STIM3 Register (Offset = Ch) [reset = 0h]

        55
      • 2.7.1.5 STIM4 Register (Offset = 10h) [reset = 0h]

        56
      • 2.7.1.6 STIM5 Register (Offset = 14h) [reset = 0h]

        57
      • 2.7.1.7 STIM6 Register (Offset = 18h) [reset = 0h]

        58
      • 2.7.1.8 STIM7 Register (Offset = 1Ch) [reset = 0h]

        59
      • 2.7.1.9 STIM8 Register (Offset = 20h) [reset = 0h]

        60
      • 2.7.1.10 STIM9 Register (Offset = 24h) [reset = 0h]

        61
      • 2.7.1.11 STIM10 Register (Offset = 28h) [reset = 0h]

        62
      • 2.7.1.12 STIM11 Register (Offset = 2Ch) [reset = 0h]

        63
      • 2.7.1.13 STIM12 Register (Offset = 30h) [reset = 0h]

        64
      • 2.7.1.14 STIM13 Register (Offset = 34h) [reset = 0h]

        65
      • 2.7.1.15 STIM14 Register (Offset = 38h) [reset = 0h]

        66
      • 2.7.1.16 STIM15 Register (Offset = 3Ch) [reset = 0h]

        67
      • 2.7.1.17 STIM16 Register (Offset = 40h) [reset = 0h]

        68
      • 2.7.1.18 STIM17 Register (Offset = 44h) [reset = 0h]

        69
      • 2.7.1.19 STIM18 Register (Offset = 48h) [reset = 0h]

        70
      • 2.7.1.20 STIM19 Register (Offset = 4Ch) [reset = 0h]

        71
      • 2.7.1.21 STIM20 Register (Offset = 50h) [reset = 0h]

        72
      • 2.7.1.22 STIM21 Register (Offset = 54h) [reset = 0h]

        73
      • 2.7.1.23 STIM22 Register (Offset = 58h) [reset = 0h]

        74
      • 2.7.1.24 STIM23 Register (Offset = 5Ch) [reset = 0h]

        75
      • 2.7.1.25 STIM24 Register (Offset = 60h) [reset = 0h]

        76
      • 2.7.1.26 STIM25 Register (Offset = 64h) [reset = 0h]

        77
      • 2.7.1.27 STIM26 Register (Offset = 68h) [reset = 0h]

        78
      • 2.7.1.28 STIM27 Register (Offset = 6Ch) [reset = 0h]

        79
      • 2.7.1.29 STIM28 Register (Offset = 70h) [reset = 0h]

        80
      • 2.7.1.30 STIM29 Register (Offset = 74h) [reset = 0h]

        81
      • 2.7.1.31 STIM30 Register (Offset = 78h) [reset = 0h]

        82
      • 2.7.1.32 STIM31 Register (Offset = 7Ch) [reset = 0h]

        83
      • 2.7.1.33 TER Register (Offset = E00h) [reset = X]

        84
      • 2.7.1.34 TPR Register (Offset = E40h) [reset = X]

        86
      • 2.7.1.35 TCR Register (Offset = E80h) [reset = X]

        87
      • 2.7.1.36 LAR Register (Offset = FB0h) [reset = X]

        89
      • 2.7.1.37 LSR Register (Offset = FB4h) [reset = X]

        90
    • 2.7.2 CPU_DWT Registers

      92
      • 2.7.2.1 CTRL Register (Offset = 0h) [reset = X]

        93
      • 2.7.2.2 CYCCNT Register (Offset = 4h) [reset = X]

        95
      • 2.7.2.3 CPICNT Register (Offset = 8h) [reset = X]

        96
      • 2.7.2.4 EXCCNT Register (Offset = Ch) [reset = X]

        97
      • 2.7.2.5 SLEEPCNT Register (Offset = 10h) [reset = X]

        98
      • 2.7.2.6 LSUCNT Register (Offset = 14h) [reset = X]

        99
      • 2.7.2.7 FOLDCNT Register (Offset = 18h) [reset = X]

        100
      • 2.7.2.8 PCSR Register (Offset = 1Ch) [reset = 0h]

        101
      • 2.7.2.9 COMP0 Register (Offset = 20h) [reset = 0h]

        102
      • 2.7.2.10 MASK0 Register (Offset = 24h) [reset = X]

        103
      • 2.7.2.11 FUNCTION0 Register (Offset = 28h) [reset = X]

        104
      • 2.7.2.12 COMP1 Register (Offset = 30h) [reset = 0h]

        106
      • 2.7.2.13 MASK1 Register (Offset = 34h) [reset = X]

        107
      • 2.7.2.14 FUNCTION1 Register (Offset = 38h) [reset = X]

        108
      • 2.7.2.15 COMP2 Register (Offset = 40h) [reset = 0h]

        110
      • 2.7.2.16 MASK2 Register (Offset = 44h) [reset = X]

        111
      • 2.7.2.17 FUNCTION2 Register (Offset = 48h) [reset = X]

        112
      • 2.7.2.18 COMP3 Register (Offset = 50h) [reset = 0h]

        113
      • 2.7.2.19 MASK3 Register (Offset = 54h) [reset = X]

        114
      • 2.7.2.20 FUNCTION3 Register (Offset = 58h) [reset = X]

        115
    • 2.7.3 CPU_FPB Registers

      117
      • 2.7.3.1 CTRL Register (Offset = 0h) [reset = X]

        118
      • 2.7.3.2 REMAP Register (Offset = 4h) [reset = X]

        119
      • 2.7.3.3 COMP0 Register (Offset = 8h) [reset = X]

        120
      • 2.7.3.4 COMP1 Register (Offset = Ch) [reset = X]

        121
      • 2.7.3.5 COMP2 Register (Offset = 10h) [reset = X]

        122
      • 2.7.3.6 COMP3 Register (Offset = 14h) [reset = X]

        123
      • 2.7.3.7 COMP4 Register (Offset = 18h) [reset = X]

        124
      • 2.7.3.8 COMP5 Register (Offset = 1Ch) [reset = X]

        125
      • 2.7.3.9 COMP6 Register (Offset = 20h) [reset = X]

        126
      • 2.7.3.10 COMP7 Register (Offset = 24h) [reset = X]

        127
    • 2.7.4 CPU_SCS Registers

      129
      • 2.7.4.1 ICTR Register (Offset = 4h) [reset = X]

        131
      • 2.7.4.2 ACTLR Register (Offset = 8h) [reset = X]

        132
      • 2.7.4.3 STCSR Register (Offset = 10h) [reset = X]

        133
      • 2.7.4.4 STRVR Register (Offset = 14h) [reset = X]

        134
      • 2.7.4.5 STCVR Register (Offset = 18h) [reset = X]

        135
      • 2.7.4.6 STCR Register (Offset = 1Ch) [reset = X]

        136
      • 2.7.4.7 NVIC_ISER0 Register (Offset = 100h) [reset = X]

        137
      • 2.7.4.8 NVIC_ISER1 Register (Offset = 104h) [reset = X]

        140
      • 2.7.4.9 NVIC_ICER0 Register (Offset = 180h) [reset = X]

        141
      • 2.7.4.10 NVIC_ICER1 Register (Offset = 184h) [reset = X]

        144
      • 2.7.4.11 NVIC_ISPR0 Register (Offset = 200h) [reset = X]

        145
      • 2.7.4.12 NVIC_ISPR1 Register (Offset = 204h) [reset = X]

        148
      • 2.7.4.13 NVIC_ICPR0 Register (Offset = 280h) [reset = X]

        149
      • 2.7.4.14 NVIC_ICPR1 Register (Offset = 284h) [reset = X]

        152
      • 2.7.4.15 NVIC_IABR0 Register (Offset = 300h) [reset = X]

        153
      • 2.7.4.16 NVIC_IABR1 Register (Offset = 304h) [reset = X]

        156
      • 2.7.4.17 NVIC_IPR0 Register (Offset = 400h) [reset = X]

        157
      • 2.7.4.18 NVIC_IPR1 Register (Offset = 404h) [reset = X]

        158
      • 2.7.4.19 NVIC_IPR2 Register (Offset = 408h) [reset = X]

        159
      • 2.7.4.20 NVIC_IPR3 Register (Offset = 40Ch) [reset = X]

        160
      • 2.7.4.21 NVIC_IPR4 Register (Offset = 410h) [reset = X]

        161
      • 2.7.4.22 NVIC_IPR5 Register (Offset = 414h) [reset = X]

        162
      • 2.7.4.23 NVIC_IPR6 Register (Offset = 418h) [reset = X]

        163
      • 2.7.4.24 NVIC_IPR7 Register (Offset = 41Ch) [reset = X]

        164
      • 2.7.4.25 NVIC_IPR8 Register (Offset = 420h) [reset = X]

        165
      • 2.7.4.26 CPUID Register (Offset = D00h) [reset = 412FC231h]

        166
      • 2.7.4.27 ICSR Register (Offset = D04h) [reset = X]

        167
      • 2.7.4.28 VTOR Register (Offset = D08h) [reset = X]

        168
      • 2.7.4.29 AIRCR Register (Offset = D0Ch) [reset = X]

        169
      • 2.7.4.30 SCR Register (Offset = D10h) [reset = X]

        170
      • 2.7.4.31 CCR Register (Offset = D14h) [reset = X]

        171
      • 2.7.4.32 SHPR1 Register (Offset = D18h) [reset = X]

        173
      • 2.7.4.33 SHPR2 Register (Offset = D1Ch) [reset = X]

        174
      • 2.7.4.34 SHPR3 Register (Offset = D20h) [reset = X]

        175
      • 2.7.4.35 SHCSR Register (Offset = D24h) [reset = X]

        176
      • 2.7.4.36 CFSR Register (Offset = D28h) [reset = X]

        178
      • 2.7.4.37 HFSR Register (Offset = D2Ch) [reset = X]

        180
      • 2.7.4.38 DFSR Register (Offset = D30h) [reset = X]

        181
      • 2.7.4.39 MMFAR Register (Offset = D34h) [reset = 0h]

        182
      • 2.7.4.40 BFAR Register (Offset = D38h) [reset = 0h]

        183
      • 2.7.4.41 AFSR Register (Offset = D3Ch) [reset = X]

        184
      • 2.7.4.42 ID_PFR0 Register (Offset = D40h) [reset = X]

        185
      • 2.7.4.43 ID_PFR1 Register (Offset = D44h) [reset = X]

        186
      • 2.7.4.44 ID_DFR0 Register (Offset = D48h) [reset = X]

        187
      • 2.7.4.45 ID_AFR0 Register (Offset = D4Ch) [reset = X]

        188
      • 2.7.4.46 ID_MMFR0 Register (Offset = D50h) [reset = 100030h]

        189
      • 2.7.4.47 ID_MMFR1 Register (Offset = D54h) [reset = X]

        190
      • 2.7.4.48 ID_MMFR2 Register (Offset = D58h) [reset = X]

        191
      • 2.7.4.49 ID_MMFR3 Register (Offset = D5Ch) [reset = X]

        192
      • 2.7.4.50 ID_ISAR0 Register (Offset = D60h) [reset = 1101110h]

        193
      • 2.7.4.51 ID_ISAR1 Register (Offset = D64h) [reset = 2111000h]

        194
      • 2.7.4.52 ID_ISAR2 Register (Offset = D68h) [reset = 21112231h]

        195
      • 2.7.4.53 ID_ISAR3 Register (Offset = D6Ch) [reset = 1111110h]

        196
      • 2.7.4.54 ID_ISAR4 Register (Offset = D70h) [reset = 1310132h]

        197
      • 2.7.4.55 CPACR Register (Offset = D88h) [reset = X]

        198
      • 2.7.4.56 DHCSR Register (Offset = DF0h) [reset = X]

        199
      • 2.7.4.57 DCRSR Register (Offset = DF4h) [reset = 0h]

        201
      • 2.7.4.58 DCRDR Register (Offset = DF8h) [reset = 0h]

        202
      • 2.7.4.59 DEMCR Register (Offset = DFCh) [reset = X]

        203
      • 2.7.4.60 STIR Register (Offset = F00h) [reset = X]

        205
    • 2.7.5 CPU_TPIU Registers

      207
      • 2.7.5.1 SSPSR Register (Offset = 0h) [reset = X]

        208
      • 2.7.5.2 CSPSR Register (Offset = 4h) [reset = X]

        209
      • 2.7.5.3 ACPR Register (Offset = 10h) [reset = X]

        210
      • 2.7.5.4 SPPR Register (Offset = F0h) [reset = X]

        211
      • 2.7.5.5 FFSR Register (Offset = 300h) [reset = X]

        212
      • 2.7.5.6 FFCR Register (Offset = 304h) [reset = X]

        213
      • 2.7.5.7 FSCR Register (Offset = 308h) [reset = X]

        214
      • 2.7.5.8 CLAIMMASK Register (Offset = FA0h) [reset = Fh]

        215
      • 2.7.5.9 CLAIMSET Register (Offset = FA0h) [reset = Fh]

        216
      • 2.7.5.10 CLAIMTAG Register (Offset = FA4h) [reset = X]

        217
      • 2.7.5.11 CLAIMCLR Register (Offset = FA4h) [reset = X]

        218
      • 2.7.5.12 DEVID Register (Offset = FC8h) [reset = CA0h]

        219
• 3 Cortex™-M3 Peripherals

  220
  • 3.1 Cortex™-M3 Peripherals Introduction

    221
  • 3.2 Functional Description

    221
    • 3.2.1 SysTick

      221
    • 3.2.2 NVIC

      222
      • 3.2.2.1 Level-Sensitive and Pulse Interrupts

        222
      • 3.2.2.2 Hardware and Software Control of Interrupts

        223
    • 3.2.3 System Control Block (SCB)

      223
    • 3.2.4 Instrumentation Trace Macrocell Unit (ITM)

      223
    • 3.2.5  Flash Patch and Breakpoint Unit (FPB)

      223
    • 3.2.6 Trace Port Interface Unit (TPIU)

      224
    • 3.2.7 Data Watchpoint and Trace Unit (DWT)

      224
• 4 Interrupts and Events

  227
  • 4.1 Exception Model

    228
    • 4.1.1 Exception States

      228
    • 4.1.2 Exception Types

      228
    • 4.1.3 Exception Handlers

      231
    • 4.1.4 Vector Table

      231
    • 4.1.5 Exception Priorities

      232
    • 4.1.6 Interrupt Priority Grouping

      232
    • 4.1.7 Exception Entry and Return

      233
      • 4.1.7.1 Exception Entry

        234
      • 4.1.7.2 Exception Return

        234
  • 4.2 Fault Handling

    235
    • 4.2.1 Fault Types

      235
    • 4.2.2 Fault Escalation and Hard Faults

      236
    • 4.2.3 Fault Status Registers and Fault Address Registers

      236
    • 4.2.4 Lockup

      236
  • 4.3 Event Fabric

    237
    • 4.3.1 Introduction

      237
    • 4.3.2 Event Fabric Overview

      238
      • 4.3.2.1 Registers

        238
  • 4.4 AON Event Fabric

    238
    • 4.4.1 Common Input Event List

      239
    • 4.4.2 Event Subscribers

      239
      • 4.4.2.1 Wake-up Controller (WUC)

        239
      • 4.4.2.2 Real-Time Clock

        240
      • 4.4.2.3 MCU Event Fabric

        240
  • 4.5 MCU Event Fabric

    240
    • 4.5.1 Common Input Event List

      241
    • 4.5.2 Event Subscribers

      244
      • 4.5.2.1 System CPU

        245
      • 4.5.2.2 NMI

        245
      • 4.5.2.3 Freeze

        245
  • 4.6 Interrupts and Events Registers

    245
    • 4.6.1 AON_EVENT Registers

      246
      • 4.6.1.1 MCUWUSEL Register (Offset = 0h) [reset = X]

        247
      • 4.6.1.2 AUXWUSEL Register (Offset = 4h) [reset = X]

        254
      • 4.6.1.3 EVTOMCUSEL Register (Offset = 8h) [reset = X]

        260
      • 4.6.1.4 RTCSEL Register (Offset = Ch) [reset = X]

        266
    • 4.6.2 EVENT Registers

      270
      • 4.6.2.1 CPUIRQSEL0 Register (Offset = 0h) [reset = X]

        273
      • 4.6.2.2 CPUIRQSEL1 Register (Offset = 4h) [reset = X]

        274
      • 4.6.2.3 CPUIRQSEL2 Register (Offset = 8h) [reset = X]

        275
      • 4.6.2.4 CPUIRQSEL3 Register (Offset = Ch) [reset = X]

        276
      • 4.6.2.5 CPUIRQSEL4 Register (Offset = 10h) [reset = X]

        277
      • 4.6.2.6 CPUIRQSEL5 Register (Offset = 14h) [reset = X]

        278
      • 4.6.2.7 CPUIRQSEL6 Register (Offset = 18h) [reset = X]

        279
      • 4.6.2.8 CPUIRQSEL7 Register (Offset = 1Ch) [reset = X]

        280
      • 4.6.2.9 CPUIRQSEL8 Register (Offset = 20h) [reset = X]

        281
      • 4.6.2.10 CPUIRQSEL9 Register (Offset = 24h) [reset = X]

        282
      • 4.6.2.11 CPUIRQSEL10 Register (Offset = 28h) [reset = X]

        283
      • 4.6.2.12 CPUIRQSEL11 Register (Offset = 2Ch) [reset = X]

        284
      • 4.6.2.13 CPUIRQSEL12 Register (Offset = 30h) [reset = X]

        285
      • 4.6.2.14 CPUIRQSEL13 Register (Offset = 34h) [reset = X]

        286
      • 4.6.2.15 CPUIRQSEL14 Register (Offset = 38h) [reset = X]

        287
      • 4.6.2.16 CPUIRQSEL15 Register (Offset = 3Ch) [reset = X]

        288
      • 4.6.2.17 CPUIRQSEL16 Register (Offset = 40h) [reset = X]

        289
      • 4.6.2.18 CPUIRQSEL17 Register (Offset = 44h) [reset = X]

        290
      • 4.6.2.19 CPUIRQSEL18 Register (Offset = 48h) [reset = X]

        291
      • 4.6.2.20 CPUIRQSEL19 Register (Offset = 4Ch) [reset = X]

        292
      • 4.6.2.21 CPUIRQSEL20 Register (Offset = 50h) [reset = X]

        293
      • 4.6.2.22 CPUIRQSEL21 Register (Offset = 54h) [reset = X]

        294
      • 4.6.2.23 CPUIRQSEL22 Register (Offset = 58h) [reset = X]

        295
      • 4.6.2.24 CPUIRQSEL23 Register (Offset = 5Ch) [reset = X]

        296
      • 4.6.2.25 CPUIRQSEL24 Register (Offset = 60h) [reset = X]

        297
      • 4.6.2.26 CPUIRQSEL25 Register (Offset = 64h) [reset = X]

        298
      • 4.6.2.27 CPUIRQSEL26 Register (Offset = 68h) [reset = X]

        299
      • 4.6.2.28 CPUIRQSEL27 Register (Offset = 6Ch) [reset = X]

        300
      • 4.6.2.29 CPUIRQSEL28 Register (Offset = 70h) [reset = X]

        301
      • 4.6.2.30 CPUIRQSEL29 Register (Offset = 74h) [reset = X]

        302
      • 4.6.2.31 CPUIRQSEL30 Register (Offset = 78h) [reset = X]

        303
      • 4.6.2.32 CPUIRQSEL31 Register (Offset = 7Ch) [reset = X]

        304
      • 4.6.2.33 CPUIRQSEL32 Register (Offset = 80h) [reset = X]

        305
      • 4.6.2.34 CPUIRQSEL33 Register (Offset = 84h) [reset = X]

        306
      • 4.6.2.35 RFCSEL0 Register (Offset = 100h) [reset = X]

        307
      • 4.6.2.36 RFCSEL1 Register (Offset = 104h) [reset = X]

        308
      • 4.6.2.37 RFCSEL2 Register (Offset = 108h) [reset = X]

        309
      • 4.6.2.38 RFCSEL3 Register (Offset = 10Ch) [reset = X]

        310
      • 4.6.2.39 RFCSEL4 Register (Offset = 110h) [reset = X]

        311
      • 4.6.2.40 RFCSEL5 Register (Offset = 114h) [reset = X]

        312
      • 4.6.2.41 RFCSEL6 Register (Offset = 118h) [reset = X]

        313
      • 4.6.2.42 RFCSEL7 Register (Offset = 11Ch) [reset = X]

        314
      • 4.6.2.43 RFCSEL8 Register (Offset = 120h) [reset = X]

        315
      • 4.6.2.44 RFCSEL9 Register (Offset = 124h) [reset = X]

        316
      • 4.6.2.45 GPT0ACAPTSEL Register (Offset = 200h) [reset = X]

        317
      • 4.6.2.46 GPT0BCAPTSEL Register (Offset = 204h) [reset = X]

        320
      • 4.6.2.47 GPT1ACAPTSEL Register (Offset = 300h) [reset = X]

        323
      • 4.6.2.48 GPT1BCAPTSEL Register (Offset = 304h) [reset = X]

        326
      • 4.6.2.49 GPT2ACAPTSEL Register (Offset = 400h) [reset = X]

        329
      • 4.6.2.50 GPT2BCAPTSEL Register (Offset = 404h) [reset = X]

        332
      • 4.6.2.51 UDMACH1SSEL Register (Offset = 508h) [reset = X]

        335
      • 4.6.2.52 UDMACH1BSEL Register (Offset = 50Ch) [reset = X]

        336
      • 4.6.2.53 UDMACH2SSEL Register (Offset = 510h) [reset = X]

        337
      • 4.6.2.54 UDMACH2BSEL Register (Offset = 514h) [reset = X]

        338
      • 4.6.2.55 UDMACH3SSEL Register (Offset = 518h) [reset = X]

        339
      • 4.6.2.56 UDMACH3BSEL Register (Offset = 51Ch) [reset = X]

        340
      • 4.6.2.57 UDMACH4SSEL Register (Offset = 520h) [reset = X]

        341
      • 4.6.2.58 UDMACH4BSEL Register (Offset = 524h) [reset = X]

        342
      • 4.6.2.59 UDMACH5SSEL Register (Offset = 528h) [reset = X]

        343
      • 4.6.2.60 UDMACH5BSEL Register (Offset = 52Ch) [reset = X]

        344
      • 4.6.2.61 UDMACH6SSEL Register (Offset = 530h) [reset = X]

        345
      • 4.6.2.62 UDMACH6BSEL Register (Offset = 534h) [reset = X]

        346
      • 4.6.2.63 UDMACH7SSEL Register (Offset = 538h) [reset = X]

        347
      • 4.6.2.64 UDMACH7BSEL Register (Offset = 53Ch) [reset = X]

        348
      • 4.6.2.65 UDMACH8SSEL Register (Offset = 540h) [reset = X]

        349
      • 4.6.2.66 UDMACH8BSEL Register (Offset = 544h) [reset = X]

        350
      • 4.6.2.67 UDMACH9SSEL Register (Offset = 548h) [reset = X]

        351
      • 4.6.2.68 UDMACH9BSEL Register (Offset = 54Ch) [reset = X]

        352
      • 4.6.2.69 UDMACH10SSEL Register (Offset = 550h) [reset = X]

        353
      • 4.6.2.70 UDMACH10BSEL Register (Offset = 554h) [reset = X]

        354
      • 4.6.2.71 UDMACH11SSEL Register (Offset = 558h) [reset = X]

        355
      • 4.6.2.72 UDMACH11BSEL Register (Offset = 55Ch) [reset = X]

        356
      • 4.6.2.73 UDMACH12SSEL Register (Offset = 560h) [reset = X]

        357
      • 4.6.2.74 UDMACH12BSEL Register (Offset = 564h) [reset = X]

        358
      • 4.6.2.75 UDMACH13BSEL Register (Offset = 56Ch) [reset = X]

        359
      • 4.6.2.76 UDMACH14BSEL Register (Offset = 574h) [reset = X]

        360
      • 4.6.2.77 UDMACH15BSEL Register (Offset = 57Ch) [reset = X]

        365
      • 4.6.2.78 UDMACH16SSEL Register (Offset = 580h) [reset = X]

        366
      • 4.6.2.79 UDMACH16BSEL Register (Offset = 584h) [reset = X]

        367
      • 4.6.2.80 UDMACH17SSEL Register (Offset = 588h) [reset = X]

        368
      • 4.6.2.81 UDMACH17BSEL Register (Offset = 58Ch) [reset = X]

        369
      • 4.6.2.82 UDMACH21SSEL Register (Offset = 5A8h) [reset = X]

        370
      • 4.6.2.83 UDMACH21BSEL Register (Offset = 5ACh) [reset = X]

        371
      • 4.6.2.84 UDMACH22SSEL Register (Offset = 5B0h) [reset = X]

        372
      • 4.6.2.85 UDMACH22BSEL Register (Offset = 5B4h) [reset = X]

        373
      • 4.6.2.86 UDMACH23SSEL Register (Offset = 5B8h) [reset = X]

        374
      • 4.6.2.87 UDMACH23BSEL Register (Offset = 5BCh) [reset = X]

        375
      • 4.6.2.88 UDMACH24SSEL Register (Offset = 5C0h) [reset = X]

        376
      • 4.6.2.89 UDMACH24BSEL Register (Offset = 5C4h) [reset = X]

        377
      • 4.6.2.90 GPT3ACAPTSEL Register (Offset = 600h) [reset = X]

        378
      • 4.6.2.91 GPT3BCAPTSEL Register (Offset = 604h) [reset = X]

        381
      • 4.6.2.92 AUXSEL0 Register (Offset = 700h) [reset = X]

        384
      • 4.6.2.93 CM3NMISEL0 Register (Offset = 800h) [reset = X]

        385
      • 4.6.2.94 I2SSTMPSEL0 Register (Offset = 900h) [reset = X]

        386
      • 4.6.2.95 FRZSEL0 Register (Offset = A00h) [reset = X]

        387
      • 4.6.2.96 SWEV Register (Offset = F00h) [reset = X]

        388
• 5 JTAG Interface

  389
  • 5.1 Top Level Debug System

    390
  • 5.2 cJTAG

    392
    • 5.2.1 JTAG Commands

      394
      • 5.2.1.1 Mandatory Commands

        396
    • 5.2.2 Programming Sequences

      396
      • 5.2.2.1 Opening Command Window

        396
      • 5.2.2.2 Changing to 4-pin Mode

        396
      • 5.2.2.3 Close Command Window

        397
  • 5.3 ICEPick™

    397
    • 5.3.1 Secondary TAPs

      397
      • 5.3.1.1 Slave DAP (CPU DAP)

        398
      • 5.3.1.2 Ordering Slave TAPs and DAPs

        398
    • 5.3.2 ICEPick™ Registers

      399
      • 5.3.2.1 IR Instructions

        399
      • 5.3.2.2 Data Shift Register

        400
      • 5.3.2.3 Instruction Register

        400
      • 5.3.2.4 Bypass Register

        400
      • 5.3.2.5 Device Identification Register

        400
      • 5.3.2.6 User Code Register

        401
      • 5.3.2.7 ICEPick™ Identification Register

        401
      • 5.3.2.8 Connect Register

        402
    • 5.3.3 ROUTER Scan Chain

      402
    • 5.3.4 TAP Routing Registers

      403
      • 5.3.4.1 ICEPick™ Control Block

        403
        • 5.3.4.1.1 All0s Register

          404
        • 5.3.4.1.2 ICEPick™ Control Register

          404
        • 5.3.4.1.3 Linking Mode Register

          404
      • 5.3.4.2 Test TAP Linking Block

        405
        • 5.3.4.2.1 Secondary Test TAP Register

          405
      • 5.3.4.3 Debug TAP Linking Block

        405
        • 5.3.4.3.1 Secondary Debug TAP Register

          405
  • 5.4 ICEMelter™

    408
  • 5.5 Serial Wire Viewer (SWV)

    408
  • 5.6 Halt In Boot (HIB)

    408
  • 5.7 Debug and Shutdown

    409
  • 5.8 Debug Features Supported Through WUC TAP

    409
  • 5.9 Profiler Register

    409
• 6 Power, Reset, and Clock Management

  411
  • 6.1 Introduction

    412
    • 6.1.1 System CPU Mode

      413
    • 6.1.2 Supply System

      413
      • 6.1.2.1 Internal DC-DC Converter and Global LDO

        414
      • 6.1.2.2 External Regulator Mode

        415
    • 6.1.3 Digital Power Partitioning

      415
      • 6.1.3.1 MCU_VD

        417
        • 6.1.3.1.1 MCU_VD Power Domains

          417
      • 6.1.3.2 AON_VD

        417
        • 6.1.3.2.1 AON_VD Power Domains

          417
    • 6.1.4 Clock Management

      417
      • 6.1.4.1 System Clocks

        417
        • 6.1.4.1.1 Controlling the Oscillators

          418
      • 6.1.4.2 Clocks in MCU_VD

        420
        • 6.1.4.2.1 Clock Gating

          422
        • 6.1.4.2.2 Scalar to GPT

          422
        • 6.1.4.2.3 Scalar to WDT

          422
      • 6.1.4.3 Clocks in AON_VD

        422
    • 6.1.5 Power Modes

      422
      • 6.1.5.1 Startup State

        423
      • 6.1.5.2 Active Mode

        424
      • 6.1.5.3 Idle Mode

        424
      • 6.1.5.4 Standby Mode

        424
      • 6.1.5.5 Shutdown Mode

        425
    • 6.1.6 Reset

      426
      • 6.1.6.1 System Resets

        426
        • 6.1.6.1.1 Clock Loss Detection

          426
        • 6.1.6.1.2 Software-Initiated System Reset

          426
        • 6.1.6.1.3 Warm Reset Converted to System Reset

          426
      • 6.1.6.2 Warm Reset

        426
      • 6.1.6.3 Software-Initiated Reset of MCU_VD

        427
      • 6.1.6.4 Reset of the MCU_VD Power Domains and Modules

        427
      • 6.1.6.5 Reset of AON_VD

        427
      • 6.1.6.6 Reset of AUX_PD

        427
  • 6.2 PRCM Registers

    427
    • 6.2.1 PRCM Registers

      428
      • 6.2.1.1 INFRCLKDIVR Register (Offset = 0h) [reset = X]

        430
      • 6.2.1.2 INFRCLKDIVS Register (Offset = 4h) [reset = X]

        431
      • 6.2.1.3 INFRCLKDIVDS Register (Offset = 8h) [reset = X]

        432
      • 6.2.1.4 VDCTL Register (Offset = Ch) [reset = X]

        433
      • 6.2.1.5 CLKLOADCTL Register (Offset = 28h) [reset = X]

        434
      • 6.2.1.6 RFCCLKG Register (Offset = 2Ch) [reset = X]

        435
      • 6.2.1.7 VIMSCLKG Register (Offset = 30h) [reset = X]

        436
      • 6.2.1.8 SECDMACLKGR Register (Offset = 3Ch) [reset = X]

        437
      • 6.2.1.9 SECDMACLKGS Register (Offset = 40h) [reset = X]

        438
      • 6.2.1.10 SECDMACLKGDS Register (Offset = 44h) [reset = X]

        439
      • 6.2.1.11 GPIOCLKGR Register (Offset = 48h) [reset = X]

        440
      • 6.2.1.12 GPIOCLKGS Register (Offset = 4Ch) [reset = X]

        441
      • 6.2.1.13 GPIOCLKGDS Register (Offset = 50h) [reset = X]

        442
      • 6.2.1.14 GPTCLKGR Register (Offset = 54h) [reset = X]

        443
      • 6.2.1.15 GPTCLKGS Register (Offset = 58h) [reset = X]

        444
      • 6.2.1.16 GPTCLKGDS Register (Offset = 5Ch) [reset = X]

        445
      • 6.2.1.17 I2CCLKGR Register (Offset = 60h) [reset = X]

        446
      • 6.2.1.18 I2CCLKGS Register (Offset = 64h) [reset = X]

        447
      • 6.2.1.19 I2CCLKGDS Register (Offset = 68h) [reset = X]

        448
      • 6.2.1.20 UARTCLKGR Register (Offset = 6Ch) [reset = X]

        449
      • 6.2.1.21 UARTCLKGS Register (Offset = 70h) [reset = X]

        450
      • 6.2.1.22 UARTCLKGDS Register (Offset = 74h) [reset = X]

        451
      • 6.2.1.23 SSICLKGR Register (Offset = 78h) [reset = X]

        452
      • 6.2.1.24 SSICLKGS Register (Offset = 7Ch) [reset = X]

        453
      • 6.2.1.25 SSICLKGDS Register (Offset = 80h) [reset = X]

        454
      • 6.2.1.26 I2SCLKGR Register (Offset = 84h) [reset = X]

        455
      • 6.2.1.27 I2SCLKGS Register (Offset = 88h) [reset = X]

        456
      • 6.2.1.28 I2SCLKGDS Register (Offset = 8Ch) [reset = X]

        457
      • 6.2.1.29 CPUCLKDIV Register (Offset = B8h) [reset = X]

        458
      • 6.2.1.30 I2SBCLKSEL Register (Offset = C8h) [reset = X]

        459
      • 6.2.1.31 GPTCLKDIV Register (Offset = CCh) [reset = X]

        460
      • 6.2.1.32 I2SCLKCTL Register (Offset = D0h) [reset = X]

        461
      • 6.2.1.33 I2SMCLKDIV Register (Offset = D4h) [reset = X]

        462
      • 6.2.1.34 I2SBCLKDIV Register (Offset = D8h) [reset = X]

        463
      • 6.2.1.35 I2SWCLKDIV Register (Offset = DCh) [reset = X]

        464
      • 6.2.1.36 SWRESET Register (Offset = 10Ch) [reset = X]

        465
      • 6.2.1.37 WARMRESET Register (Offset = 110h) [reset = X]

        466
      • 6.2.1.38 PDCTL0 Register (Offset = 12Ch) [reset = X]

        467
      • 6.2.1.39 PDCTL0RFC Register (Offset = 130h) [reset = X]

        468
      • 6.2.1.40 PDCTL0SERIAL Register (Offset = 134h) [reset = X]

        469
      • 6.2.1.41 PDCTL0PERIPH Register (Offset = 138h) [reset = X]

        470
      • 6.2.1.42 PDSTAT0 Register (Offset = 140h) [reset = X]

        471
      • 6.2.1.43 PDSTAT0RFC Register (Offset = 144h) [reset = X]

        472
      • 6.2.1.44 PDSTAT0SERIAL Register (Offset = 148h) [reset = X]

        473
      • 6.2.1.45 PDSTAT0PERIPH Register (Offset = 14Ch) [reset = X]

        474
      • 6.2.1.46 PDCTL1 Register (Offset = 17Ch) [reset = X]

        475
      • 6.2.1.47 PDCTL1CPU Register (Offset = 184h) [reset = X]

        476
      • 6.2.1.48 PDCTL1RFC Register (Offset = 188h) [reset = X]

        477
      • 6.2.1.49 PDCTL1VIMS Register (Offset = 18Ch) [reset = X]

        478
      • 6.2.1.50 PDSTAT1 Register (Offset = 194h) [reset = X]

        479
      • 6.2.1.51 PDSTAT1BUS Register (Offset = 198h) [reset = X]

        480
      • 6.2.1.52 PDSTAT1RFC Register (Offset = 19Ch) [reset = X]

        481
      • 6.2.1.53 PDSTAT1CPU Register (Offset = 1A0h) [reset = X]

        482
      • 6.2.1.54 PDSTAT1VIMS Register (Offset = 1A4h) [reset = X]

        483
      • 6.2.1.55 RFCMODESEL Register (Offset = 1D0h) [reset = X]

        484
      • 6.2.1.56 RAMRETEN Register (Offset = 224h) [reset = X]

        485
      • 6.2.1.57 RAMHWOPT Register (Offset = 250h) [reset = X]

        486
    • 6.2.2 AON_SYSCTL Registers

      488
      • 6.2.2.1 PWRCTL Register (Offset = 0h) [reset = X]

        489
      • 6.2.2.2 RESETCTL Register (Offset = 4h) [reset = X]

        490
      • 6.2.2.3 SLEEPCTL Register (Offset = 8h) [reset = X]

        492
    • 6.2.3 AON_WUC Registers

      493
      • 6.2.3.1 MCUCLK Register (Offset = 0h) [reset = X]

        494
      • 6.2.3.2 AUXCLK Register (Offset = 4h) [reset = X]

        495
      • 6.2.3.3 MCUCFG Register (Offset = 8h) [reset = X]

        496
      • 6.2.3.4 AUXCFG Register (Offset = Ch) [reset = X]

        497
      • 6.2.3.5 AUXCTL Register (Offset = 10h) [reset = X]

        498
      • 6.2.3.6 PWRSTAT Register (Offset = 14h) [reset = X]

        499
      • 6.2.3.7 SHUTDOWN Register (Offset = 18h) [reset = X]

        500
      • 6.2.3.8 CTL0 Register (Offset = 20h) [reset = X]

        501
      • 6.2.3.9 CTL1 Register (Offset = 24h) [reset = X]

        502
      • 6.2.3.10 RECHARGECFG Register (Offset = 30h) [reset = X]

        503
      • 6.2.3.11 RECHARGESTAT Register (Offset = 34h) [reset = X]

        505
      • 6.2.3.12 OSCCFG Register (Offset = 38h) [reset = X]

        506
      • 6.2.3.13 JTAGCFG Register (Offset = 40h) [reset = X]

        507
      • 6.2.3.14 JTAGUSERCODE Register (Offset = 44h) [reset = B99A02Fh]

        508
    • 6.2.4 DDI_0_OSC Registers

      509
      • 6.2.4.1 CTL0 Register (Offset = 0h) [reset = X]

        510
      • 6.2.4.2 CTL1 Register (Offset = 4h) [reset = X]

        512
      • 6.2.4.3 RADCEXTCFG Register (Offset = 8h) [reset = X]

        513
      • 6.2.4.4 AMPCOMPCTL Register (Offset = Ch) [reset = X]

        514
      • 6.2.4.5 AMPCOMPTH1 Register (Offset = 10h) [reset = X]

        515
      • 6.2.4.6 AMPCOMPTH2 Register (Offset = 14h) [reset = X]

        516
      • 6.2.4.7 ANABYPASSVAL1 Register (Offset = 18h) [reset = X]

        517
      • 6.2.4.8 ANABYPASSVAL2 Register (Offset = 1Ch) [reset = X]

        518
      • 6.2.4.9 ATESTCTL Register (Offset = 20h) [reset = X]

        519
      • 6.2.4.10 ADCDOUBLERNANOAMPCTL Register (Offset = 24h) [reset = X]

        520
      • 6.2.4.11 XOSCHFCTL Register (Offset = 28h) [reset = X]

        521
      • 6.2.4.12 LFOSCCTL Register (Offset = 2Ch) [reset = X]

        522
      • 6.2.4.13 RCOSCHFCTL Register (Offset = 30h) [reset = X]

        523
      • 6.2.4.14 STAT0 Register (Offset = 34h) [reset = X]

        524
      • 6.2.4.15 STAT1 Register (Offset = 38h) [reset = X]

        526
      • 6.2.4.16 STAT2 Register (Offset = 3Ch) [reset = X]

        528
• 7 Versatile Instruction Memory System (VIMS)

  529
  • 7.1 VIMS Configurations

    531
    • 7.1.1 VIMS Modes

      531
      • 7.1.1.1 GPRAM Mode

        531
      • 7.1.1.2 Off Mode

        532
      • 7.1.1.3 Cache Mode

        532
      • 7.1.1.4 Split Mode

        533
    • 7.1.2 VIMS Flash Line Buffering

      534
    • 7.1.3 VIMS Arbitration

      534
    • 7.1.4 VIMS Cache TAG Prefetch

      534
  • 7.2 VIMS Software (SW) Remarks

    534
    • 7.2.1 Flash Program or Update

      534
    • 7.2.2 VIMS Retention

      534
      • 7.2.2.1 Mode 1

        535
      • 7.2.2.2 Mode 2

        535
  • 7.3 VIMS Registers

    537
    • 7.3.1 STAT Register (Offset = 0h) [reset = X]

      538
    • 7.3.2 CTL Register (Offset = 4h) [reset = X]

      539
  • 7.4 ROM

    540
  • 7.5 EEFUSE

    540
  • 7.6 FLASH

    540
    • 7.6.1 FLASH Memory Protection

      540
    • 7.6.2 Memory Programming

      540
      • 7.6.2.1 Disabling Debug Access

        541
    • 7.6.3 FLASH Memory Programming

      541
    • 7.6.4 FLASH Read Timings

      541
    • 7.6.5 Power Mode Operations

      541
  • 7.7 VIMS Registers

    541
    • 7.7.1 FLASHMEM Registers

      542
    • 7.7.2 FLASH Registers

      543
      • 7.7.2.1 STAT Register (Offset = 1Ch) [reset = X]

        546
      • 7.7.2.2 CFG Register (Offset = 24h) [reset = X]

        547
      • 7.7.2.3 SYSCODE_START Register (Offset = 28h) [reset = X]

        548
      • 7.7.2.4 FLASH_SIZE Register (Offset = 2Ch) [reset = X]

        549
      • 7.7.2.5 FWLOCK Register (Offset = 3Ch) [reset = X]

        550
      • 7.7.2.6 FWFLAG Register (Offset = 40h) [reset = X]

        551
      • 7.7.2.7 EFUSE Register (Offset = 1000h) [reset = X]

        552
      • 7.7.2.8 EFUSEADDR Register (Offset = 1004h) [reset = X]

        553
      • 7.7.2.9 DATAUPPER Register (Offset = 1008h) [reset = X]

        554
      • 7.7.2.10 DATALOWER Register (Offset = 100Ch) [reset = X]

        555
      • 7.7.2.11 EFUSECFG Register (Offset = 1010h) [reset = X]

        556
      • 7.7.2.12 EFUSESTAT Register (Offset = 1014h) [reset = X]

        557
      • 7.7.2.13 ACC Register (Offset = 1018h) [reset = X]

        558
      • 7.7.2.14 BOUNDARY Register (Offset = 101Ch) [reset = X]

        559
      • 7.7.2.15 EFUSEFLAG Register (Offset = 1020h) [reset = X]

        560
      • 7.7.2.16 EFUSEKEY Register (Offset = 1024h) [reset = X]

        561
      • 7.7.2.17 EFUSERELEASE Register (Offset = 1028h) [reset = 0h]

        562
      • 7.7.2.18 EFUSEPINS Register (Offset = 102Ch) [reset = X]

        563
      • 7.7.2.19 EFUSECRA Register (Offset = 1030h) [reset = X]

        564
      • 7.7.2.20 EFUSEREAD Register (Offset = 1034h) [reset = X]

        565
      • 7.7.2.21 EFUSEPROGRAM Register (Offset = 1038h) [reset = X]

        566
      • 7.7.2.22 EFUSEERROR Register (Offset = 103Ch) [reset = X]

        567
      • 7.7.2.23 SINGLEBIT Register (Offset = 1040h) [reset = X]

        568
      • 7.7.2.24 TWOBIT Register (Offset = 1044h) [reset = X]

        569
      • 7.7.2.25 SELFTESTCYC Register (Offset = 1048h) [reset = X]

        570
      • 7.7.2.26 SELFTESTSIGN Register (Offset = 104Ch) [reset = X]

        571
      • 7.7.2.27 FRDCTL Register (Offset = 2000h) [reset = X]

        572
      • 7.7.2.28 FSPRD Register (Offset = 2004h) [reset = X]

        573
      • 7.7.2.29 FEDACCTL1 Register (Offset = 2008h) [reset = X]

        574
      • 7.7.2.30 FEDACSTAT Register (Offset = 201Ch) [reset = X]

        575
      • 7.7.2.31 FBPROT Register (Offset = 2030h) [reset = X]

        576
      • 7.7.2.32 FBSE Register (Offset = 2034h) [reset = X]

        577
      • 7.7.2.33 FBBUSY Register (Offset = 2038h) [reset = X]

        578
      • 7.7.2.34 FBAC Register (Offset = 203Ch) [reset = X]

        579
      • 7.7.2.35 FBFALLBACK Register (Offset = 2040h) [reset = X]

        580
      • 7.7.2.36 FBPRDY Register (Offset = 2044h) [reset = X]

        581
      • 7.7.2.37 FPAC1 Register (Offset = 2048h) [reset = X]

        582
      • 7.7.2.38 FPAC2 Register (Offset = 204Ch) [reset = X]

        583
      • 7.7.2.39 FMAC Register (Offset = 2050h) [reset = X]

        584
      • 7.7.2.40 FMSTAT Register (Offset = 2054h) [reset = X]

        585
      • 7.7.2.41 FLOCK Register (Offset = 2064h) [reset = X]

        586
      • 7.7.2.42 FVREADCT Register (Offset = 2080h) [reset = X]

        587
      • 7.7.2.43 FVHVCT1 Register (Offset = 2084h) [reset = X]

        588
      • 7.7.2.44 FVHVCT2 Register (Offset = 2088h) [reset = X]

        589
      • 7.7.2.45 FVHVCT3 Register (Offset = 208Ch) [reset = X]

        590
      • 7.7.2.46 FVNVCT Register (Offset = 2090h) [reset = X]

        591
      • 7.7.2.47 FVSLP Register (Offset = 2094h) [reset = X]

        592
      • 7.7.2.48 FVWLCT Register (Offset = 2098h) [reset = X]

        593
      • 7.7.2.49 FEFUSECTL Register (Offset = 209Ch) [reset = X]

        594
      • 7.7.2.50 FEFUSESTAT Register (Offset = 20A0h) [reset = X]

        595
      • 7.7.2.51 FEFUSEDATA Register (Offset = 20A4h) [reset = X]

        596
      • 7.7.2.52 FSEQPMP Register (Offset = 20A8h) [reset = X]

        597
      • 7.7.2.53 FBSTROBES Register (Offset = 2100h) [reset = X]

        598
      • 7.7.2.54 FPSTROBES Register (Offset = 2104h) [reset = X]

        599
      • 7.7.2.55 FBMODE Register (Offset = 2108h) [reset = X]

        600
      • 7.7.2.56 FTCR Register (Offset = 210Ch) [reset = X]

        601
      • 7.7.2.57 FADDR Register (Offset = 2110h) [reset = X]

        602
      • 7.7.2.58 FTCTL Register (Offset = 211Ch) [reset = X]

        603
      • 7.7.2.59 FWPWRITE0 Register (Offset = 2120h) [reset = FFFFFFFFh]

        604
      • 7.7.2.60 FWPWRITE1 Register (Offset = 2124h) [reset = FFFFFFFFh]

        605
      • 7.7.2.61 FWPWRITE2 Register (Offset = 2128h) [reset = FFFFFFFFh]

        606
      • 7.7.2.62 FWPWRITE3 Register (Offset = 212Ch) [reset = FFFFFFFFh]

        607
      • 7.7.2.63 FWPWRITE4 Register (Offset = 2130h) [reset = FFFFFFFFh]

        608
      • 7.7.2.64 FWPWRITE5 Register (Offset = 2134h) [reset = FFFFFFFFh]

        609
      • 7.7.2.65 FWPWRITE6 Register (Offset = 2138h) [reset = FFFFFFFFh]

        610
      • 7.7.2.66 FWPWRITE7 Register (Offset = 213Ch) [reset = FFFFFFFFh]

        611
      • 7.7.2.67 FWPWRITE_ECC Register (Offset = 2140h) [reset = FFFFFFFFh]

        612
      • 7.7.2.68 FSWSTAT Register (Offset = 2144h) [reset = X]

        613
      • 7.7.2.69 FSM_GLBCTL Register (Offset = 2200h) [reset = X]

        614
      • 7.7.2.70 FSM_STATE Register (Offset = 2204h) [reset = X]

        615
      • 7.7.2.71 FSM_STAT Register (Offset = 2208h) [reset = X]

        616
      • 7.7.2.72 FSM_CMD Register (Offset = 220Ch) [reset = X]

        617
      • 7.7.2.73 FSM_PE_OSU Register (Offset = 2210h) [reset = X]

        618
      • 7.7.2.74 FSM_VSTAT Register (Offset = 2214h) [reset = X]

        619
      • 7.7.2.75 FSM_PE_VSU Register (Offset = 2218h) [reset = X]

        620
      • 7.7.2.76 FSM_CMP_VSU Register (Offset = 221Ch) [reset = X]

        621
      • 7.7.2.77 FSM_EX_VAL Register (Offset = 2220h) [reset = X]

        622
      • 7.7.2.78 FSM_RD_H Register (Offset = 2224h) [reset = X]

        623
      • 7.7.2.79 FSM_P_OH Register (Offset = 2228h) [reset = X]

        624
      • 7.7.2.80 FSM_ERA_OH Register (Offset = 222Ch) [reset = X]

        625
      • 7.7.2.81 FSM_SAV_PPUL Register (Offset = 2230h) [reset = X]

        626
      • 7.7.2.82 FSM_PE_VH Register (Offset = 2234h) [reset = X]

        627
      • 7.7.2.83 FSM_PRG_PW Register (Offset = 2240h) [reset = X]

        628
      • 7.7.2.84 FSM_ERA_PW Register (Offset = 2244h) [reset = X]

        629
      • 7.7.2.85 FSM_SAV_ERA_PUL Register (Offset = 2254h) [reset = X]

        630
      • 7.7.2.86 FSM_TIMER Register (Offset = 2258h) [reset = X]

        631
      • 7.7.2.87 FSM_MODE Register (Offset = 225Ch) [reset = X]

        632
      • 7.7.2.88 FSM_PGM Register (Offset = 2260h) [reset = X]

        633
      • 7.7.2.89 FSM_ERA Register (Offset = 2264h) [reset = X]

        634
      • 7.7.2.90 FSM_PRG_PUL Register (Offset = 2268h) [reset = X]

        635
      • 7.7.2.91 FSM_ERA_PUL Register (Offset = 226Ch) [reset = X]

        636
      • 7.7.2.92 FSM_STEP_SIZE Register (Offset = 2270h) [reset = X]

        637
      • 7.7.2.93 FSM_PUL_CNTR Register (Offset = 2274h) [reset = X]

        638
      • 7.7.2.94 FSM_EC_STEP_HEIGHT Register (Offset = 2278h) [reset = X]

        639
      • 7.7.2.95 FSM_ST_MACHINE Register (Offset = 227Ch) [reset = X]

        640
      • 7.7.2.96 FSM_FLES Register (Offset = 2280h) [reset = X]

        641
      • 7.7.2.97 FSM_WR_ENA Register (Offset = 2288h) [reset = X]

        642
      • 7.7.2.98 FSM_ACC_PP Register (Offset = 228Ch) [reset = X]

        643
      • 7.7.2.99 FSM_ACC_EP Register (Offset = 2290h) [reset = X]

        644
      • 7.7.2.100 FSM_ADDR Register (Offset = 22A0h) [reset = X]

        645
      • 7.7.2.101 FSM_SECTOR Register (Offset = 22A4h) [reset = X]

        646
      • 7.7.2.102 FMC_REV_ID Register (Offset = 22A8h) [reset = 0h]

        647
      • 7.7.2.103 FSM_ERR_ADDR Register (Offset = 22ACh) [reset = X]

        648
      • 7.7.2.104 FSM_PGM_MAXPUL Register (Offset = 22B0h) [reset = X]

        649
      • 7.7.2.105 FSM_EXECUTE Register (Offset = 22B4h) [reset = X]

        650
      • 7.7.2.106 FSM_SECTOR1 Register (Offset = 22C0h) [reset = FFFFFFFFh]

        651
      • 7.7.2.107 FSM_SECTOR2 Register (Offset = 22C4h) [reset = X]

        652
      • 7.7.2.108 FSM_BSLE0 Register (Offset = 22E0h) [reset = X]

        653
      • 7.7.2.109 FSM_BSLE1 Register (Offset = 22E4h) [reset = X]

        654
      • 7.7.2.110 FSM_BSLP0 Register (Offset = 22F0h) [reset = X]

        655
      • 7.7.2.111 FSM_BSLP1 Register (Offset = 22F4h) [reset = X]

        656
      • 7.7.2.112 FCFG_BANK Register (Offset = 2400h) [reset = X]

        657
      • 7.7.2.113 FCFG_WRAPPER Register (Offset = 2404h) [reset = X]

        658
      • 7.7.2.114 FCFG_BNK_TYPE Register (Offset = 2408h) [reset = X]

        659
      • 7.7.2.115 FCFG_B0_START Register (Offset = 2410h) [reset = X]

        660
      • 7.7.2.116 FCFG_B1_START Register (Offset = 2414h) [reset = X]

        661
      • 7.7.2.117 FCFG_B2_START Register (Offset = 2418h) [reset = X]

        662
      • 7.7.2.118 FCFG_B3_START Register (Offset = 241Ch) [reset = X]

        663
      • 7.7.2.119 FCFG_B4_START Register (Offset = 2420h) [reset = X]

        664
      • 7.7.2.120 FCFG_B5_START Register (Offset = 2424h) [reset = X]

        665
      • 7.7.2.121 FCFG_B6_START Register (Offset = 2428h) [reset = X]

        666
      • 7.7.2.122 FCFG_B7_START Register (Offset = 242Ch) [reset = X]

        667
      • 7.7.2.123 FCFG_B0_SSIZE0 Register (Offset = 2430h) [reset = X]

        668
  • 7.8 ROM Functions

    669
  • 7.9 SRAM

    670
• 8 Bootloader

  671
  • 8.1 Bootloader Functionality

    672
    • 8.1.1 Bootloader Disabling

      672
    • 8.1.2 Bootloader Backdoor

      672
  • 8.2 Bootloader Interfaces

    672
    • 8.2.1 Packet Handling

      673
      • 8.2.1.1 Packet Acknowledge and Not-Acknowledge Bytes

        674
    • 8.2.2 Transport Layer

      674
      • 8.2.2.1 UART Transport

        675
        • 8.2.2.1.1 UART Baud Rate Auto-Detection

          675
      • 8.2.2.2 SSI Transport

        675
    • 8.2.3 Serial Bus Commands

      676
      • 8.2.3.1 COMMAND_PING

        677
      • 8.2.3.2 COMMAND_DOWNLOAD

        678
      • 8.2.3.3 COMMAND_SEND_DATA

        678
      • 8.2.3.4 COMMAND_SECTOR_ERASE

        678
      • 8.2.3.5 COMMAND_GET_STATUS

        679
      • 8.2.3.6 COMMAND_RESET

        680
      • 8.2.3.7 COMMAND_GET_CHIP_ID

        680
      • 8.2.3.8 COMMAND_CRC32

        681
      • 8.2.3.9 COMMAND_BANK_ERASE

        682
      • 8.2.3.10 COMMAND_CHIP_ERASE

        682
      • 8.2.3.11 COMMAND_SET_CCFG

        682
• 9 Device Configuration

  685
  • 9.1 Customer Configuration (CCFG)

    686
    • 9.1.1 CCFG Registers

      687
      • 9.1.1.1 MODE_CONF_1 Register (Offset = FACh) [reset = FFFBFFFFh]

        688
      • 9.1.1.2 SIZE_AND_DIS_FLAGS Register (Offset = FB0h) [reset = FFFFFFFFh]

        689
      • 9.1.1.3 MODE_CONF Register (Offset = FB4h) [reset = FFFFFFFFh]

        690
      • 9.1.1.4 VOLT_LOAD_0 Register (Offset = FB8h) [reset = FFFFFFFFh]

        692
      • 9.1.1.5 VOLT_LOAD_1 Register (Offset = FBCh) [reset = FFFFFFFFh]

        693
      • 9.1.1.6 RTC_OFFSET Register (Offset = FC0h) [reset = FFFFFFFFh]

        694
      • 9.1.1.7 FREQ_OFFSET Register (Offset = FC4h) [reset = FFFFFFFFh]

        695
      • 9.1.1.8 IEEE_MAC_0 Register (Offset = FC8h) [reset = FFFFFFFFh]

        696
      • 9.1.1.9 IEEE_MAC_1 Register (Offset = FCCh) [reset = FFFFFFFFh]

        697
      • 9.1.1.10 IEEE_BLE_0 Register (Offset = FD0h) [reset = FFFFFFFFh]

        698
      • 9.1.1.11 IEEE_BLE_1 Register (Offset = FD4h) [reset = FFFFFFFFh]

        699
      • 9.1.1.12 BL_CONFIG Register (Offset = FD8h) [reset = C5FFFFFFh]

        700
      • 9.1.1.13 ERASE_CONF Register (Offset = FDCh) [reset = FFFFFFFFh]

        701
      • 9.1.1.14 CCFG_TI_OPTIONS Register (Offset = FE0h) [reset = FFFFFFC5h]

        702
      • 9.1.1.15 CCFG_TAP_DAP_0 Register (Offset = FE4h) [reset = FFC5C5C5h]

        703
      • 9.1.1.16 CCFG_TAP_DAP_1 Register (Offset = FE8h) [reset = FFC5C5C5h]

        704
      • 9.1.1.17 IMAGE_VALID_CONF Register (Offset = FECh) [reset = FFFFFFFFh]

        705
      • 9.1.1.18 CCFG_PROT_31_0 Register (Offset = FF0h) [reset = FFFFFFFFh]

        706
      • 9.1.1.19 CCFG_PROT_63_32 Register (Offset = FF4h) [reset = FFFFFFFFh]

        708
      • 9.1.1.20 CCFG_PROT_95_64 Register (Offset = FF8h) [reset = FFFFFFFFh]

        710
      • 9.1.1.21 CCFG_PROT_127_96 Register (Offset = FFCh) [reset = FFFFFFFFh]

        712
  • 9.2 Factory Configuration (FCFG)

    713
    • 9.2.1 FCFG1 Registers

      714
      • 9.2.1.1 CONFIG_RF_FRONTEND_DIV5 Register (Offset = C4h) [reset = FFFFFFFFh]

        716
      • 9.2.1.2 CONFIG_RF_FRONTEND_DIV6 Register (Offset = C8h) [reset = FFFFFFFFh]

        717
      • 9.2.1.3 CONFIG_RF_FRONTEND_DIV10 Register (Offset = CCh) [reset = FFFFFFFFh]

        718
      • 9.2.1.4 CONFIG_RF_FRONTEND_DIV12 Register (Offset = D0h) [reset = FFFFFFFFh]

        719
      • 9.2.1.5 CONFIG_RF_FRONTEND_DIV15 Register (Offset = D4h) [reset = FFFFFFFFh]

        720
      • 9.2.1.6 CONFIG_RF_FRONTEND_DIV30 Register (Offset = D8h) [reset = FFFFFFFFh]

        721
      • 9.2.1.7 CONFIG_SYNTH_DIV5 Register (Offset = DCh) [reset = FFFFFFFFh]

        722
      • 9.2.1.8 CONFIG_SYNTH_DIV6 Register (Offset = E0h) [reset = FFFFFFFFh]

        723
      • 9.2.1.9 CONFIG_SYNTH_DIV10 Register (Offset = E4h) [reset = FFFFFFFFh]

        724
      • 9.2.1.10 CONFIG_SYNTH_DIV12 Register (Offset = E8h) [reset = FFFFFFFFh]

        725
      • 9.2.1.11 CONFIG_SYNTH_DIV15 Register (Offset = ECh) [reset = FFFFFFFFh]

        726
      • 9.2.1.12 CONFIG_SYNTH_DIV30 Register (Offset = F0h) [reset = FFFFFFFFh]

        727
      • 9.2.1.13 CONFIG_MISC_ADC_DIV5 Register (Offset = F4h) [reset = FFFFFFFFh]

        728
      • 9.2.1.14 CONFIG_MISC_ADC_DIV6 Register (Offset = F8h) [reset = FFFFFFFFh]

        729
      • 9.2.1.15 CONFIG_MISC_ADC_DIV10 Register (Offset = FCh) [reset = FFFFFFFFh]

        730
      • 9.2.1.16 CONFIG_MISC_ADC_DIV12 Register (Offset = 100h) [reset = FFFFFFFFh]

        731
      • 9.2.1.17 CONFIG_MISC_ADC_DIV15 Register (Offset = 104h) [reset = FFFFFFFFh]

        732
      • 9.2.1.18 CONFIG_MISC_ADC_DIV30 Register (Offset = 108h) [reset = FFFFFFFFh]

        733
      • 9.2.1.19 SHDW_DIE_ID_0 Register (Offset = 118h) [reset = 0h]

        734
      • 9.2.1.20 SHDW_DIE_ID_1 Register (Offset = 11Ch) [reset = 0h]

        735
      • 9.2.1.21 SHDW_DIE_ID_2 Register (Offset = 120h) [reset = 0h]

        736
      • 9.2.1.22 SHDW_DIE_ID_3 Register (Offset = 124h) [reset = 0h]

        737
      • 9.2.1.23 SHDW_OSC_BIAS_LDO_TRIM Register (Offset = 138h) [reset = 0h]

        738
      • 9.2.1.24 SHDW_ANA_TRIM Register (Offset = 13Ch) [reset = 0h]

        739
      • 9.2.1.25 FLASH_NUMBER Register (Offset = 164h) [reset = 0h]

        740
      • 9.2.1.26 FLASH_COORDINATE Register (Offset = 16Ch) [reset = 0h]

        741
      • 9.2.1.27 FLASH_E_P Register (Offset = 170h) [reset = 17331A33h]

        742
      • 9.2.1.28 FLASH_C_E_P_R Register (Offset = 174h) [reset = X]

        743
      • 9.2.1.29 FLASH_P_R_PV Register (Offset = 178h) [reset = X]

        744
      • 9.2.1.30 FLASH_EH_SEQ Register (Offset = 17Ch) [reset = X]

        745
      • 9.2.1.31 FLASH_VHV_E Register (Offset = 180h) [reset = X]

        746
      • 9.2.1.32 FLASH_PP Register (Offset = 184h) [reset = X]

        747
      • 9.2.1.33 FLASH_PROG_EP Register (Offset = 188h) [reset = FA00010h]

        748
      • 9.2.1.34 FLASH_ERA_PW Register (Offset = 18Ch) [reset = FA0h]

        749
      • 9.2.1.35 FLASH_VHV Register (Offset = 190h) [reset = X]

        750
      • 9.2.1.36 FLASH_VHV_PV Register (Offset = 194h) [reset = X]

        751
      • 9.2.1.37 FLASH_V Register (Offset = 198h) [reset = 0h]

        752
      • 9.2.1.38 USER_ID Register (Offset = 294h) [reset = 0h]

        753
      • 9.2.1.39 FLASH_OTP_DATA3 Register (Offset = 2B0h) [reset = X]

        754
      • 9.2.1.40 ANA2_TRIM Register (Offset = 2B4h) [reset = X]

        755
      • 9.2.1.41 LDO_TRIM Register (Offset = 2B8h) [reset = X]

        757
      • 9.2.1.42 MAC_BLE_0 Register (Offset = 2E8h) [reset = 0h]

        758
      • 9.2.1.43 MAC_BLE_1 Register (Offset = 2ECh) [reset = 0h]

        759
      • 9.2.1.44 MAC_15_4_0 Register (Offset = 2F0h) [reset = 0h]

        760
      • 9.2.1.45 MAC_15_4_1 Register (Offset = 2F4h) [reset = 0h]

        761
      • 9.2.1.46 FLASH_OTP_DATA4 Register (Offset = 308h) [reset = X]

        762
      • 9.2.1.47 MISC_TRIM Register (Offset = 30Ch) [reset = FFFFFF33h]

        764
      • 9.2.1.48 RCOSC_HF_TEMPCOMP Register (Offset = 310h) [reset = X]

        765
      • 9.2.1.49 TRIM_CAL_REVISION Register (Offset = 314h) [reset = 0h]

        766
      • 9.2.1.50 ICEPICK_DEVICE_ID Register (Offset = 318h) [reset = 8B99A02Fh]

        767
      • 9.2.1.51 FCFG1_REVISION Register (Offset = 31Ch) [reset = 23h]

        768
      • 9.2.1.52 MISC_OTP_DATA Register (Offset = 320h) [reset = X]

        769
      • 9.2.1.53 IOCONF Register (Offset = 344h) [reset = 7FFFFF8000h]

        770
      • 9.2.1.54 CONFIG_IF_ADC Register (Offset = 34Ch) [reset = X]

        771
      • 9.2.1.55 CONFIG_OSC_TOP Register (Offset = 350h) [reset = X]

        772
      • 9.2.1.56 CONFIG_RF_FRONTEND Register (Offset = 354h) [reset = X]

        773
      • 9.2.1.57 CONFIG_SYNTH Register (Offset = 358h) [reset = FFFFF000h]

        774
      • 9.2.1.58 SOC_ADC_ABS_GAIN Register (Offset = 35Ch) [reset = 0h]

        775
      • 9.2.1.59 SOC_ADC_REL_GAIN Register (Offset = 360h) [reset = 0h]

        776
      • 9.2.1.60 SOC_ADC_EXT_GAIN Register (Offset = 364h) [reset = 0h]

        777
      • 9.2.1.61 SOC_ADC_OFFSET_INT Register (Offset = 368h) [reset = 0h]

        778
      • 9.2.1.62 SOC_ADC_REF_TRIM_AND_OFFSET_EXT Register (Offset = 36Ch) [reset = 300080h]

        779
      • 9.2.1.63 AMPCOMP_TH1 Register (Offset = 370h) [reset = FF7B828Eh]

        780
      • 9.2.1.64 AMPCOMP_TH2 Register (Offset = 374h) [reset = X]

        781
      • 9.2.1.65 AMPCOMP_CTRL1 Register (Offset = 378h) [reset = FF183F47h]

        782
      • 9.2.1.66 ANABYPASS_VALUE2 Register (Offset = 37Ch) [reset = FFFFC3FFh]

        783
      • 9.2.1.67 CONFIG_MISC_ADC Register (Offset = 380h) [reset = FFFC014Dh]

        784
      • 9.2.1.68 VOLT_TRIM Register (Offset = 388h) [reset = FFFFFFE0h]

        785
      • 9.2.1.69 OSC_CONF Register (Offset = 38Ch) [reset = X]

        786
      • 9.2.1.70 CAP_TRIM Register (Offset = 394h) [reset = FFFFFFFFh]

        787
      • 9.2.1.71 MISC_OTP_DATA_1 Register (Offset = 398h) [reset = X]

        788
      • 9.2.1.72 PWD_CURR_20C Register (Offset = 39Ch) [reset = 80BA608h]

        789
      • 9.2.1.73 PWD_CURR_35C Register (Offset = 3A0h) [reset = C10A50Ah]

        790
      • 9.2.1.74 PWD_CURR_50C Register (Offset = 3A4h) [reset = 1218A20Dh]

        791
      • 9.2.1.75 PWD_CURR_65C Register (Offset = 3A8h) [reset = 1C259C14h]

        792
      • 9.2.1.76 PWD_CURR_80C Register (Offset = 3ACh) [reset = 2E3B9021h]

        793
      • 9.2.1.77 PWD_CURR_95C Register (Offset = 3B0h) [reset = 4C627A3Bh]

        794
      • 9.2.1.78 PWD_CURR_110C Register (Offset = 3B4h) [reset = 789E706Bh]

        795
      • 9.2.1.79 PWD_CURR_125C Register (Offset = 3B8h) [reset = ADE1809Ah]

        796
• 10 Cryptography

  797
  • 10.1 AES Cryptoprocessor Overview

    798
    • 10.1.1 Functional Description

      798
      • 10.1.1.1 Debug Capabilities

        799
      • 10.1.1.2 Exception Handling

        799
    • 10.1.2 Power Management and Sleep Modes

      799
    • 10.1.3 Hardware Description

      799
      • 10.1.3.1 AHB Slave Bus

        799
      • 10.1.3.2 AHB Master Bus

        799
      • 10.1.3.3 Interrupts

        800
    • 10.1.4 Module Description

      800
      • 10.1.4.1 Introduction

        800
      • 10.1.4.2 Module Memory Map

        800
      • 10.1.4.3 DMA Controller

        802
        • 10.1.4.3.1 Internal Operation

          803
        • 10.1.4.3.2 Supported DMA Operations

          804
      • 10.1.4.4 Master Control and Select

        804
        • 10.1.4.4.1 Algorithm Select

          805
        • 10.1.4.4.2 Master PROT Enable

          805
        • 10.1.4.4.3 Software Reset

          805
      • 10.1.4.5 AES Engine

        805
        • 10.1.4.5.1 Second Key Registers (internal, but clearable)

          806
        • 10.1.4.5.2 AES Initialization Vector (IV) Registers

          807
        • 10.1.4.5.3 AES I/O Buffer Control, Mode, and Length Registers

          807
        • 10.1.4.5.4 Data Input/Output Registers

          808
        • 10.1.4.5.5 TAG Registers

          809
      • 10.1.4.6 Key Area Registers

        809
        • 10.1.4.6.1 Key Write Area Register

          809
        • 10.1.4.6.2 Key Written Area Register

          809
        • 10.1.4.6.3 Key Size Register

          809
        • 10.1.4.6.4 Key Read Area Register

          810
    • 10.1.5 Performance

      810
      • 10.1.5.1 Introduction

        810
      • 10.1.5.2 Performance

        811
    • 10.1.6 Programming Guidelines

      811
      • 10.1.6.1 One Time Initialization After a Reset

        811
      • 10.1.6.2 DMAC and Master Control

        811
        • 10.1.6.2.1 Regular Use

          811
        • 10.1.6.2.2 Interrupting DMA Transfers

          812
        • 10.1.6.2.3 Interrupts and Harware and Software Synchronization

          812
      • 10.1.6.3 Encryption and Decryption

        812
        • 10.1.6.3.1 Data Format and Byte Order

          813
        • 10.1.6.3.2 Key Store

          814
        • 10.1.6.3.3 Basic AES Modes

          814
        • 10.1.6.3.4 CBC-MAC

          817
        • 10.1.6.3.5 AES-CCM

          818
      • 10.1.6.4 Exceptions Handling

        819
        • 10.1.6.4.1 Soft Reset

          819
        • 10.1.6.4.2 External Port Errors

          819
        • 10.1.6.4.3 Key Store Errors

          820
    • 10.1.7 Conventions and Compliances

      820
      • 10.1.7.1 Conventions Used in This Manual

        820
        • 10.1.7.1.1 Acronyms

          820
        • 10.1.7.1.2 Terminology

          821
        • 10.1.7.1.3 Formulae and Nomenclature

          822
      • 10.1.7.2 Compliances

        822
  • 10.2 Cryptography Registers

    822
    • 10.2.1 CRYPTO Registers

      823
      • 10.2.1.1 DMACH0CTL Register (Offset = 0h) [reset = X]

        824
      • 10.2.1.2 DMACH0EXTADDR Register (Offset = 4h) [reset = X]

        825
      • 10.2.1.3 DMACH0LEN Register (Offset = Ch) [reset = X]

        826
      • 10.2.1.4 DMASTAT Register (Offset = 18h) [reset = X]

        827
      • 10.2.1.5 DMASWRESET Register (Offset = 1Ch) [reset = X]

        828
      • 10.2.1.6 DMACH1CTL Register (Offset = 20h) [reset = X]

        829
      • 10.2.1.7 DMACH1EXTADDR Register (Offset = 24h) [reset = X]

        830
      • 10.2.1.8 DMACH1LEN Register (Offset = 2Ch) [reset = X]

        831
      • 10.2.1.9 DMABUSCFG Register (Offset = 78h) [reset = X]

        832
      • 10.2.1.10 DMAPORTERR Register (Offset = 7Ch) [reset = X]

        833
      • 10.2.1.11 DMAHWVER Register (Offset = FCh) [reset = X]

        834
      • 10.2.1.12 KEYWRITEAREA Register (Offset = 400h) [reset = X]

        835
      • 10.2.1.13 KEYWRITTENAREA Register (Offset = 404h) [reset = X]

        837
      • 10.2.1.14 KEYSIZE Register (Offset = 408h) [reset = X]

        839
      • 10.2.1.15 KEYREADAREA Register (Offset = 40Ch) [reset = X]

        840
      • 10.2.1.16 AESKEY2_0 to AESKEY2_3 Register (Offset = 500h to 50Ch) [reset = X]

        841
      • 10.2.1.17 AESKEY3_0 to AESKEY3_3 Register (Offset = 510h to 51Ch) [reset = X]

        842
      • 10.2.1.18 AESIV_0 to AESIV_3 Register (Offset = 540h to 54Ch) [reset = X]

        843
      • 10.2.1.19 AESCTL Register (Offset = 550h) [reset = X]

        844
      • 10.2.1.20 AESDATALEN0 Register (Offset = 554h) [reset = X]

        846
      • 10.2.1.21 AESDATALEN1 Register (Offset = 558h) [reset = X]

        847
      • 10.2.1.22 AESAUTHLEN Register (Offset = 55Ch) [reset = X]

        848
      • 10.2.1.23 AESDATAOUT0 Register (Offset = 560h) [reset = X]

        849
      • 10.2.1.24 AESDATAIN0 Register (Offset = 560h) [reset = X]

        850
      • 10.2.1.25 AESDATAOUT1 Register (Offset = 564h) [reset = X]

        851
      • 10.2.1.26 AESDATAIN1 Register (Offset = 564h) [reset = X]

        852
      • 10.2.1.27 AESDATAOUT2 Register (Offset = 568h) [reset = X]

        853
      • 10.2.1.28 AESDATAIN2 Register (Offset = 568h) [reset = X]

        854
      • 10.2.1.29 AESDATAOUT3 Register (Offset = 56Ch) [reset = X]

        855
      • 10.2.1.30 AESDATAIN3 Register (Offset = 56Ch) [reset = X]

        856
      • 10.2.1.31 AESTAGOUT_0 to AESTAGOUT_3 Register (Offset = 570h to 57Ch) [reset = X]

        857
      • 10.2.1.32 ALGSEL Register (Offset = 700h) [reset = X]

        858
      • 10.2.1.33 DMAPROTCTL Register (Offset = 704h) [reset = X]

        859
      • 10.2.1.34 SWRESET Register (Offset = 740h) [reset = X]

        860
      • 10.2.1.35 IRQTYPE Register (Offset = 780h) [reset = X]

        861
      • 10.2.1.36 IRQEN Register (Offset = 784h) [reset = X]

        862
      • 10.2.1.37 IRQCLR Register (Offset = 788h) [reset = X]

        863
      • 10.2.1.38 IRQSET Register (Offset = 78Ch) [reset = X]

        864
      • 10.2.1.39 IRQSTAT Register (Offset = 790h) [reset = X]

        865
      • 10.2.1.40 HWVER Register (Offset = 7FCh) [reset = 91118778h]

        866
• 11 I/O Control

  867
  • 11.1 Introduction

    868
  • 11.2 IOC Overview

    868
  • 11.3 I/O Mapping and Configuration

    869
    • 11.3.1 Basic I/O Mapping

      869
    • 11.3.2 MAP AUXIO from the Sensor Controller to DIO Pin

      869
      • 11.3.2.1 Control External LNA/PA (Range Extender) With I/Os

        869
    • 11.3.3 Map 32-kHz System Clock (LF Clock) to DIO/PIN

      870
  • 11.4 Edge Detection on Pin (DIO)

    870
    • 11.4.1 Configure DIO as GPIO Input to Generate Interrupt on EDGE DETECT

      870
  • 11.5 AON IOC State Latching When Powering Off the MCU Domain

    870
  • 11.6 Unused I/O Pins

    871
  • 11.7 GPIO

    871
  • 11.8 I/O Pin Mapping

    872
  • 11.9 Peripheral PORTIDs

    873
  • 11.10 I/O Pin

    873
    • 11.10.1 Physical Pin

      873
    • 11.10.2 Pin Configuration

      874
  • 11.11 I/O Control Registers

    875
    • 11.11.1 AON_IOC Registers

      876
      • 11.11.1.1 IOSTRMIN Register (Offset = 0h) [reset = X]

        877
      • 11.11.1.2 IOSTRMED Register (Offset = 4h) [reset = X]

        878
      • 11.11.1.3 IOSTRMAX Register (Offset = 8h) [reset = X]

        879
      • 11.11.1.4 IOCLATCH Register (Offset = Ch) [reset = X]

        880
      • 11.11.1.5 CLK32KCTL Register (Offset = 10h) [reset = X]

        881
    • 11.11.2 IOC Registers

      883
      • 11.11.2.1 IOCFG0 Register (Offset = 0h) [reset = X]

        884
      • 11.11.2.2 IOCFG1 Register (Offset = 4h) [reset = X]

        888
      • 11.11.2.3 IOCFG2 Register (Offset = 8h) [reset = X]

        892
      • 11.11.2.4 IOCFG3 Register (Offset = Ch) [reset = X]

        896
      • 11.11.2.5 IOCFG4 Register (Offset = 10h) [reset = X]

        900
      • 11.11.2.6 IOCFG5 Register (Offset = 14h) [reset = X]

        904
      • 11.11.2.7 IOCFG6 Register (Offset = 18h) [reset = X]

        908
      • 11.11.2.8 IOCFG7 Register (Offset = 1Ch) [reset = X]

        912
      • 11.11.2.9 IOCFG8 Register (Offset = 20h) [reset = X]

        916
      • 11.11.2.10 IOCFG9 Register (Offset = 24h) [reset = X]

        920
      • 11.11.2.11 IOCFG10 Register (Offset = 28h) [reset = X]

        924
      • 11.11.2.12 IOCFG11 Register (Offset = 2Ch) [reset = X]

        928
      • 11.11.2.13 IOCFG12 Register (Offset = 30h) [reset = X]

        932
      • 11.11.2.14 IOCFG13 Register (Offset = 34h) [reset = X]

        936
      • 11.11.2.15 IOCFG14 Register (Offset = 38h) [reset = X]

        940
      • 11.11.2.16 IOCFG15 Register (Offset = 3Ch) [reset = X]

        944
      • 11.11.2.17 IOCFG16 Register (Offset = 40h) [reset = X]

        948
      • 11.11.2.18 IOCFG17 Register (Offset = 44h) [reset = X]

        952
      • 11.11.2.19 IOCFG18 Register (Offset = 48h) [reset = X]

        956
      • 11.11.2.20 IOCFG19 Register (Offset = 4Ch) [reset = X]

        960
      • 11.11.2.21 IOCFG20 Register (Offset = 50h) [reset = X]

        964
      • 11.11.2.22 IOCFG21 Register (Offset = 54h) [reset = X]

        968
      • 11.11.2.23 IOCFG22 Register (Offset = 58h) [reset = X]

        972
      • 11.11.2.24 IOCFG23 Register (Offset = 5Ch) [reset = X]

        976
      • 11.11.2.25 IOCFG24 Register (Offset = 60h) [reset = X]

        980
      • 11.11.2.26 IOCFG25 Register (Offset = 64h) [reset = X]

        984
      • 11.11.2.27 IOCFG26 Register (Offset = 68h) [reset = X]

        988
      • 11.11.2.28 IOCFG27 Register (Offset = 6Ch) [reset = X]

        992
      • 11.11.2.29 IOCFG28 Register (Offset = 70h) [reset = X]

        996
      • 11.11.2.30 IOCFG29 Register (Offset = 74h) [reset = X]

        1000
      • 11.11.2.31 IOCFG30 Register (Offset = 78h) [reset = X]

        1004
      • 11.11.2.32 IOCFG31 Register (Offset = 7Ch) [reset = X]

        1008
    • 11.11.3 GPIO Registers

      1012
      • 11.11.3.1 DOUT3_0 Register (Offset = 0h) [reset = X]

        1013
      • 11.11.3.2 DOUT7_4 Register (Offset = 4h) [reset = X]

        1014
      • 11.11.3.3 DOUT11_8 Register (Offset = 8h) [reset = X]

        1015
      • 11.11.3.4 DOUT15_12 Register (Offset = Ch) [reset = X]

        1016
      • 11.11.3.5 DOUT19_16 Register (Offset = 10h) [reset = X]

        1017
      • 11.11.3.6 DOUT23_20 Register (Offset = 14h) [reset = X]

        1018
      • 11.11.3.7 DOUT27_24 Register (Offset = 18h) [reset = X]

        1019
      • 11.11.3.8 DOUT31_28 Register (Offset = 1Ch) [reset = X]

        1020
      • 11.11.3.9 DOUT31_0 Register (Offset = 80h) [reset = X]

        1021
      • 11.11.3.10 DOUTSET31_0 Register (Offset = 90h) [reset = X]

        1023
      • 11.11.3.11 DOUTCLR31_0 Register (Offset = A0h) [reset = X]

        1025
      • 11.11.3.12 DOUTTGL31_0 Register (Offset = B0h) [reset = X]

        1027
      • 11.11.3.13 DIN31_0 Register (Offset = C0h) [reset = X]

        1029
      • 11.11.3.14 DOE31_0 Register (Offset = D0h) [reset = X]

        1031
      • 11.11.3.15 EVFLAGS31_0 Register (Offset = E0h) [reset = X]

        1033
• 12 Micro Direct Memory Access (µDMA)

  1035
  • 12.1 μDMA Introduction

    1036
  • 12.2 Block Diagram

    1036
  • 12.3 Functional Description

    1037
    • 12.3.1 Channel Assignments

      1037
    • 12.3.2 Priority

      1039
    • 12.3.3 Arbitration Size

      1039
    • 12.3.4 Request Types

      1039
      • 12.3.4.1 Single Request

        1040
      • 12.3.4.2 Burst Request

        1040
    • 12.3.5 Channel Configuration

      1040
    • 12.3.6 Transfer Modes

      1041
      • 12.3.6.1 Stop Mode

        1041
      • 12.3.6.2 Basic Mode

        1041
      • 12.3.6.3 Auto Mode

        1042
      • 12.3.6.4 Ping-Pong

        1042
      • 12.3.6.5 Memory Scatter-Gather Mode

        1043
      • 12.3.6.6 Peripheral Scatter-Gather Mode

        1047
    • 12.3.7 Transfer Size and Increments

      1050
    • 12.3.8 Peripheral Interface

      1050
    • 12.3.9 Software Request

      1050
    • 12.3.10 Interrupts and Errors

      1051
  • 12.4 Initialization and Configuration

    1051
    • 12.4.1 Module Initialization

      1051
    • 12.4.2 Configuring a Memory-to-Memory Transfer

      1052
      • 12.4.2.1 Configure the Channel Attributes

        1052
      • 12.4.2.2 Configure the Channel Control Structure

        1052
      • 12.4.2.3 Start the Transfer

        1052
    • 12.4.3 Configuring Channel Assignments

      1052
  • 12.5 µDMA Registers

    1052
    • 12.5.1 UDMA Registers

      1053
      • 12.5.1.1 STATUS Register (Offset = 0h) [reset = X]

        1054
      • 12.5.1.2 CFG Register (Offset = 4h) [reset = X]

        1055
      • 12.5.1.3 CTRL Register (Offset = 8h) [reset = X]

        1056
      • 12.5.1.4 ALTCTRL Register (Offset = Ch) [reset = 200h]

        1057
      • 12.5.1.5 WAITONREQ Register (Offset = 10h) [reset = FFFF1EFFh]

        1058
      • 12.5.1.6 SOFTREQ Register (Offset = 14h) [reset = X]

        1059
      • 12.5.1.7 SETBURST Register (Offset = 18h) [reset = X]

        1060
      • 12.5.1.8 CLEARBURST Register (Offset = 1Ch) [reset = X]

        1061
      • 12.5.1.9 SETREQMASK Register (Offset = 20h) [reset = X]

        1062
      • 12.5.1.10 CLEARREQMASK Register (Offset = 24h) [reset = X]

        1063
      • 12.5.1.11 SETCHANNELEN Register (Offset = 28h) [reset = X]

        1064
      • 12.5.1.12 CLEARCHANNELEN Register (Offset = 2Ch) [reset = X]

        1065
      • 12.5.1.13 SETCHNLPRIALT Register (Offset = 30h) [reset = X]

        1066
      • 12.5.1.14 CLEARCHNLPRIALT Register (Offset = 34h) [reset = X]

        1067
      • 12.5.1.15 SETCHNLPRIORITY Register (Offset = 38h) [reset = X]

        1068
      • 12.5.1.16 CLEARCHNLPRIORITY Register (Offset = 3Ch) [reset = X]

        1069
      • 12.5.1.17 ERROR Register (Offset = 4Ch) [reset = X]

        1070
      • 12.5.1.18 REQDONE Register (Offset = 504h) [reset = X]

        1071
      • 12.5.1.19 DONEMASK Register (Offset = 520h) [reset = X]

        1072
• 13 Timers

  1073
  • 13.1 General-Purpose Timers

    1074
  • 13.2 Block Diagram

    1074
  • 13.3 Functional Description

    1075
    • 13.3.1 GPTM Reset Conditions

      1076
    • 13.3.2 Timer Modes

      1076
      • 13.3.2.1 One-Shot or Periodic Timer Mode

        1077
      • 13.3.2.2 Input Edge-Count Mode

        1078
      • 13.3.2.3 Input Edge-Time Mode

        1079
      • 13.3.2.4 PWM Mode

        1080
    • 13.3.3 Wait-for-Trigger Mode

      1083
    • 13.3.4 Synchronizing GP Timer Blocks

      1083
    • 13.3.5 Accessing Concatenated 16- and 32-Bit GPTM Register Values

      1084
  • 13.4 Initialization and Configuration

    1084
    • 13.4.1 One-Shot and Periodic Timer Modes

      1084
    • 13.4.2 Input Edge-Count Mode

      1085
    • 13.4.3 Input Edge-Timing Mode

      1085
    • 13.4.4 PWM Mode

      1086
    • 13.4.5 Producing DMA Trigger

      1086
  • 13.5 General-Purpose Timer Registers

    1086
    • 13.5.1 GPT Registers

      1087
      • 13.5.1.1 CFG Register (Offset = 0h) [reset = X]

        1088
      • 13.5.1.2 TAMR Register (Offset = 4h) [reset = X]

        1089
      • 13.5.1.3 TBMR Register (Offset = 8h) [reset = X]

        1091
      • 13.5.1.4 CTL Register (Offset = Ch) [reset = X]

        1093
      • 13.5.1.5 SYNC Register (Offset = 10h) [reset = X]

        1095
      • 13.5.1.6 IMR Register (Offset = 18h) [reset = X]

        1096
      • 13.5.1.7 RIS Register (Offset = 1Ch) [reset = X]

        1098
      • 13.5.1.8 MIS Register (Offset = 20h) [reset = X]

        1100
      • 13.5.1.9 ICLR Register (Offset = 24h) [reset = X]

        1102
      • 13.5.1.10 TAILR Register (Offset = 28h) [reset = FFFFFFFFh]

        1103
      • 13.5.1.11 TBILR Register (Offset = 2Ch) [reset = FFFFh]

        1104
      • 13.5.1.12 TAMATCHR Register (Offset = 30h) [reset = FFFFFFFFh]

        1105
      • 13.5.1.13 TBMATCHR Register (Offset = 34h) [reset = FFFFh]

        1106
      • 13.5.1.14 TAPR Register (Offset = 38h) [reset = X]

        1107
      • 13.5.1.15 TBPR Register (Offset = 3Ch) [reset = X]

        1108
      • 13.5.1.16 TAPMR Register (Offset = 40h) [reset = X]

        1109
      • 13.5.1.17 TBPMR Register (Offset = 44h) [reset = X]

        1110
      • 13.5.1.18 TAR Register (Offset = 48h) [reset = FFFFFFFFh]

        1111
      • 13.5.1.19 TBR Register (Offset = 4Ch) [reset = FFFFh]

        1112
      • 13.5.1.20 TAV Register (Offset = 50h) [reset = FFFFFFFFh]

        1113
      • 13.5.1.21 TBV Register (Offset = 54h) [reset = FFFFh]

        1114
      • 13.5.1.22 RTCPD Register (Offset = 58h) [reset = X]

        1115
      • 13.5.1.23 TAPS Register (Offset = 5Ch) [reset = X]

        1116
      • 13.5.1.24 TBPS Register (Offset = 60h) [reset = X]

        1117
      • 13.5.1.25 TAPV Register (Offset = 64h) [reset = X]

        1118
      • 13.5.1.26 TBPV Register (Offset = 68h) [reset = X]

        1119
      • 13.5.1.27 DMAEV Register (Offset = 6Ch) [reset = X]

        1120
      • 13.5.1.28 ADCEV Register (Offset = 70h) [reset = X]

        1121
      • 13.5.1.29 VERSION Register (Offset = FB0h) [reset = 400h]

        1122
      • 13.5.1.30 ANDCCP Register (Offset = FB4h) [reset = X]

        1123
• 14 Real-Time Clock

  1124
  • 14.1 Introduction

    1125
  • 14.2 Functional Specifications

    1125
    • 14.2.1 Functional Overview

      1125
    • 14.2.2 Free-Running Counter

      1125
    • 14.2.3 Channels

      1125
    • 14.2.4 Events

      1126
  • 14.3 RTC Registers

    1126
    • 14.3.1 Register Access

      1126
    • 14.3.2 Entering and Wakeup From Sleep

      1127
    • 14.3.3 [AON_RTC:SYNC] Register

      1127
  • 14.4 Real-Time Clock Registers

    1127
    • 14.4.1 AON_RTC Registers

      1128
      • 14.4.1.1 CTL Register (Offset = 0h) [reset = X]

        1129
      • 14.4.1.2 EVFLAGS Register (Offset = 4h) [reset = X]

        1131
      • 14.4.1.3 SEC Register (Offset = 8h) [reset = X]

        1132
      • 14.4.1.4 SUBSEC Register (Offset = Ch) [reset = X]

        1133
      • 14.4.1.5 SUBSECINC Register (Offset = 10h) [reset = X]

        1134
      • 14.4.1.6 CHCTL Register (Offset = 14h) [reset = X]

        1135
      • 14.4.1.7 CH0CMP Register (Offset = 18h) [reset = X]

        1136
      • 14.4.1.8 CH1CMP Register (Offset = 1Ch) [reset = X]

        1137
      • 14.4.1.9 CH2CMP Register (Offset = 20h) [reset = X]

        1138
      • 14.4.1.10 CH2CMPINC Register (Offset = 24h) [reset = X]

        1139
      • 14.4.1.11 CH1CAPT Register (Offset = 28h) [reset = X]

        1140
      • 14.4.1.12 SYNC Register (Offset = 2Ch) [reset = X]

        1141
• 15 Watchdog Timer

  1142
  • 15.1 WDT Introduction

    1143
  • 15.2 WDT Functional Description

    1143
  • 15.3 WDT Initialization and Configuration

    1144
  • 15.4 Watchdog Timer Registers

    1144
    • 15.4.1 WDT Registers

      1145
      • 15.4.1.1 LOAD Register (Offset = 0h) [reset = FFFFFFFFh]

        1146
      • 15.4.1.2 VALUE Register (Offset = 4h) [reset = FFFFFFFFh]

        1147
      • 15.4.1.3 CTL Register (Offset = 8h) [reset = X]

        1148
      • 15.4.1.4 ICR Register (Offset = Ch) [reset = X]

        1149
      • 15.4.1.5 RIS Register (Offset = 10h) [reset = X]

        1150
      • 15.4.1.6 MIS Register (Offset = 14h) [reset = X]

        1151
      • 15.4.1.7 TEST Register (Offset = 418h) [reset = X]

        1152
      • 15.4.1.8 INT_CAUS Register (Offset = 41Ch) [reset = X]

        1153
      • 15.4.1.9 LOCK Register (Offset = C00h) [reset = X]

        1154
• 16 Random Number Generator

  1155
  • 16.1 Overview

    1156
  • 16.2 Block Diagram

    1156
  • 16.3 TRNG Software Reset

    1157
  • 16.4 Interrupt Requests

    1157
  • 16.5 TRNG Operation Description

    1158
    • 16.5.1 TRNG Shutdown

      1158
    • 16.5.2 TRNG Alarms

      1159
    • 16.5.3 TRNG Entropy

      1159
  • 16.6 TRNG Low-level Programing Guide

    1160
    • 16.6.1 Initialization

      1160
      • 16.6.1.1 Interfacing Modules

        1160
      • 16.6.1.2 TRNG Main Sequence

        1160
      • 16.6.1.3 TRNG Operating Modes

        1161
        • 16.6.1.3.1 Polling Mode

          1161
        • 16.6.1.3.2 Interrupt Mode

          1162
  • 16.7 Random Number Generator

    1162
    • 16.7.1 TRNG Registers

      1163
      • 16.7.1.1 OUT0 Register (Offset = 0h) [reset = X]

        1164
      • 16.7.1.2 OUT1 Register (Offset = 4h) [reset = X]

        1165
      • 16.7.1.3 IRQFLAGSTAT Register (Offset = 8h) [reset = X]

        1166
      • 16.7.1.4 IRQFLAGMASK Register (Offset = Ch) [reset = X]

        1167
      • 16.7.1.5 IRQFLAGCLR Register (Offset = 10h) [reset = X]

        1168
      • 16.7.1.6 CTL Register (Offset = 14h) [reset = X]

        1169
      • 16.7.1.7 CFG0 Register (Offset = 18h) [reset = X]

        1170
      • 16.7.1.8 ALARMCNT Register (Offset = 1Ch) [reset = X]

        1171
      • 16.7.1.9 FROEN Register (Offset = 20h) [reset = X]

        1172
      • 16.7.1.10 FRODETUNE Register (Offset = 24h) [reset = X]

        1173
      • 16.7.1.11 ALARMMASK Register (Offset = 28h) [reset = X]

        1174
      • 16.7.1.12 ALARMSTOP Register (Offset = 2Ch) [reset = X]

        1175
      • 16.7.1.13 LFSR0 Register (Offset = 30h) [reset = X]

        1176
      • 16.7.1.14 LFSR1 Register (Offset = 34h) [reset = X]

        1177
      • 16.7.1.15 LFSR2 Register (Offset = 38h) [reset = X]

        1178
      • 16.7.1.16 HWOPT Register (Offset = 78h) [reset = X]

        1179
      • 16.7.1.17 HWVER0 Register (Offset = 7Ch) [reset = X]

        1180
      • 16.7.1.18 IRQSTATMASK Register (Offset = 1FD8h) [reset = X]

        1181
      • 16.7.1.19 HWVER1 Register (Offset = 1FE0h) [reset = X]

        1182
      • 16.7.1.20 IRQSET Register (Offset = 1FECh) [reset = X]

        1183
      • 16.7.1.21 SWRESET Register (Offset = 1FF0h) [reset = X]

        1184
      • 16.7.1.22 IRQSTAT Register (Offset = 1FF8h) [reset = X]

        1185
• 17 AUX – Sensor Controller with Digital and Analog Peripherals

  1186
  • 17.1 Introduction

    1187
    • 17.1.1 AUX Hardware Overview

      1188
  • 17.2 Memory Mapping

    1189
    • 17.2.1 Alias of Commonly Used Registers

      1189
  • 17.3 IO Mapping

    1191
  • 17.4 Modules

    1191
    • 17.4.1 Sensor Controller

      1191
      • 17.4.1.1 Introduction

        1191
      • 17.4.1.2 Registers

        1192
      • 17.4.1.3 Interfaces

        1192
      • 17.4.1.4 Events, Sleep, and Clock Management

        1192
        • 17.4.1.4.1 WEV1, WEV0 , and SLEEP Instructions

          1192
      • 17.4.1.5 Instruction Set

        1193
        • 17.4.1.5.1 Memory Access

          1193
        • 17.4.1.5.2 I/O Access

          1193
        • 17.4.1.5.3 I/O Bit Access

          1194
        • 17.4.1.5.4 Arithmetic and Logical Operations

          1194
        • 17.4.1.5.5 Shift Operations

          1195
        • 17.4.1.5.6 Flow Control

          1196
        • 17.4.1.5.7 Events, Sleep, and Power Management

          1197
        • 17.4.1.5.8 Miscellaneous Instructions

          1198
        • 17.4.1.5.9 Reset

          1199
        • 17.4.1.5.10 Limitations

          1199
      • 17.4.1.6 Sensor Controller Control and Status

        1199
        • 17.4.1.6.1 Single-Stepping and Debugging the Sensor Controller

          1199
      • 17.4.1.7 Running a Program

        1200
        • 17.4.1.7.1 Use Case – Periodic Wake Up

          1200
    • 17.4.2 GPIO Control

      1200
      • 17.4.2.1 Event Control

        1200
        • 17.4.2.1.1 Software-Defined Events

          1201
        • 17.4.2.1.2 Sensor Controller Events

          1201
        • 17.4.2.1.3 Events to AON Event Fabric

          1201
        • 17.4.2.1.4 Events to MCU

          1202
    • 17.4.3 AUX Timers

      1203
    • 17.4.4 Time-to-Digital Converter

      1203
      • 17.4.4.1 Configuration

        1203
      • 17.4.4.2 Clocks

        1203
        • 17.4.4.2.1 Start and Stop Source

          1203
        • 17.4.4.2.2 Saturation

          1204
        • 17.4.4.2.3 Prescaler

          1204
      • 17.4.4.3 Performing a Measurement

        1204
    • 17.4.5 Semaphores

      1204
    • 17.4.6 Oscillator Configuration Interface (DDI)

      1204
    • 17.4.7 Analog Configuration Interface (ADI)

      1204
    • 17.4.8 Analog MUX

      1205
    • 17.4.9 ADC

      1205
      • 17.4.9.1 Introduction

        1205
      • 17.4.9.2 ADC Reference

        1205
      • 17.4.9.3 Configuration

        1206
        • 17.4.9.3.1 Sample Mode and Sample Duration

          1206
        • 17.4.9.3.2  Input Signal Scaling

          1206
        • 17.4.9.3.3 ADC Enable

          1206
        • 17.4.9.3.4 Digital Core

          1206
        • 17.4.9.3.5 ADC Core Clock

          1206
      • 17.4.9.4 Sampling

        1206
      • 17.4.9.5 FIFO

        1207
      • 17.4.9.6 Interrupts and Events

        1207
      • 17.4.9.7 DMA Usage

        1207
      • 17.4.9.8 Usage Example – Single Shot ADC Measurement

        1207
        • 17.4.9.8.1 Enable Interface Clocks and ADC Clocks

          1207
        • 17.4.9.8.2 Configure the ADC Registers

          1207
        • 17.4.9.8.3 Sampling

          1208
    • 17.4.10 Comparators

      1208
    • 17.4.11 Current source

      1208
  • 17.5 Power Management

    1208
    • 17.5.1 Startup

      1208
    • 17.5.2 Power Mode Management

      1208
      • 17.5.2.1 Active Mode

        1208
      • 17.5.2.2 Power Down

        1209
      • 17.5.2.3 Power Off

        1209
    • 17.5.3 Wakeup Events

      1209
    • 17.5.4 MCU Bus Connection

      1210
  • 17.6 Clock Management

    1210
    • 17.6.1 System Clocks

      1210
      • 17.6.1.1 Active Mode

        1210
      • 17.6.1.2 Power Down

        1211
    • 17.6.2 Sensor Controller Clock

      1211
    • 17.6.3 Peripheral Clocks

      1211
  • 17.7 Use Cases

    1211
    • 17.7.1 RTC Calibration

      1211
    • 17.7.2 Capacitive Sensing

      1211
    • 17.7.3 Pulse Counting

      1211
  • 17.8 AUX – Sensor Controller Registers

    1211
    • 17.8.1 AUX_AIODIO Registers

      1212
      • 17.8.1.1 GPIODOUT Register (Offset = 0h) [reset = X]

        1213
      • 17.8.1.2 IOMODE Register (Offset = 4h) [reset = X]

        1214
      • 17.8.1.3 GPIODIN Register (Offset = 8h) [reset = X]

        1216
      • 17.8.1.4 GPIODOUTSET Register (Offset = Ch) [reset = X]

        1217
      • 17.8.1.5 GPIODOUTCLR Register (Offset = 10h) [reset = X]

        1218
      • 17.8.1.6 GPIODOUTTGL Register (Offset = 14h) [reset = X]

        1219
      • 17.8.1.7 GPIODIE Register (Offset = 18h) [reset = X]

        1220
    • 17.8.2 AUX_TDC Registers

      1221
      • 17.8.2.1 CTL Register (Offset = 0h) [reset = X]

        1222
      • 17.8.2.2 STAT Register (Offset = 4h) [reset = X]

        1223
      • 17.8.2.3 RESULT Register (Offset = 8h) [reset = X]

        1224
      • 17.8.2.4 SATCFG Register (Offset = Ch) [reset = X]

        1225
      • 17.8.2.5 TRIGSRC Register (Offset = 10h) [reset = X]

        1226
      • 17.8.2.6 TRIGCNT Register (Offset = 14h) [reset = X]

        1229
      • 17.8.2.7 TRIGCNTLOAD Register (Offset = 18h) [reset = X]

        1230
      • 17.8.2.8 TRIGCNTCFG Register (Offset = 1Ch) [reset = X]

        1231
      • 17.8.2.9 PRECTL Register (Offset = 20h) [reset = X]

        1232
      • 17.8.2.10 PRECNT Register (Offset = 24h) [reset = X]

        1234
    • 17.8.3 AUX_EVCTL Registers

      1235
      • 17.8.3.1 VECCFG0 Register (Offset = 0h) [reset = X]

        1236
      • 17.8.3.2 VECCFG1 Register (Offset = 4h) [reset = X]

        1239
      • 17.8.3.3 SCEWEVSEL Register (Offset = 8h) [reset = X]

        1242
      • 17.8.3.4 EVTOAONFLAGS Register (Offset = Ch) [reset = X]

        1243
      • 17.8.3.5 EVTOAONPOL Register (Offset = 10h) [reset = X]

        1244
      • 17.8.3.6 DMACTL Register (Offset = 14h) [reset = X]

        1245
      • 17.8.3.7 SWEVSET Register (Offset = 18h) [reset = X]

        1246
      • 17.8.3.8 EVSTAT0 Register (Offset = 1Ch) [reset = X]

        1247
      • 17.8.3.9 EVSTAT1 Register (Offset = 20h) [reset = X]

        1248
      • 17.8.3.10 EVTOMCUPOL Register (Offset = 24h) [reset = X]

        1249
      • 17.8.3.11 EVTOMCUFLAGS Register (Offset = 28h) [reset = X]

        1251
      • 17.8.3.12 COMBEVTOMCUMASK Register (Offset = 2Ch) [reset = X]

        1252
      • 17.8.3.13 VECFLAGS Register (Offset = 34h) [reset = X]

        1253
      • 17.8.3.14 EVTOMCUFLAGSCLR Register (Offset = 38h) [reset = X]

        1254
      • 17.8.3.15 EVTOAONFLAGSCLR Register (Offset = 3Ch) [reset = X]

        1255
      • 17.8.3.16 VECFLAGSCLR Register (Offset = 40h) [reset = X]

        1256
    • 17.8.4 AON_WUC Registers

      1257
      • 17.8.4.1 MCUCLK Register (Offset = 0h) [reset = X]

        1258
      • 17.8.4.2 AUXCLK Register (Offset = 4h) [reset = X]

        1259
      • 17.8.4.3 MCUCFG Register (Offset = 8h) [reset = X]

        1260
      • 17.8.4.4 AUXCFG Register (Offset = Ch) [reset = X]

        1261
      • 17.8.4.5 AUXCTL Register (Offset = 10h) [reset = X]

        1262
      • 17.8.4.6 PWRSTAT Register (Offset = 14h) [reset = X]

        1263
      • 17.8.4.7 SHUTDOWN Register (Offset = 18h) [reset = X]

        1264
      • 17.8.4.8 CTL0 Register (Offset = 20h) [reset = X]

        1265
      • 17.8.4.9 CTL1 Register (Offset = 24h) [reset = X]

        1266
      • 17.8.4.10 RECHARGECFG Register (Offset = 30h) [reset = X]

        1267
      • 17.8.4.11 RECHARGESTAT Register (Offset = 34h) [reset = X]

        1269
      • 17.8.4.12 OSCCFG Register (Offset = 38h) [reset = X]

        1270
      • 17.8.4.13 JTAGCFG Register (Offset = 40h) [reset = X]

        1271
      • 17.8.4.14 JTAGUSERCODE Register (Offset = 44h) [reset = B99A02Fh]

        1272
    • 17.8.5 AUX_TIMER Registers

      1273
      • 17.8.5.1 T0CFG Register (Offset = 0h) [reset = X]

        1274
      • 17.8.5.2 T1CFG Register (Offset = 4h) [reset = X]

        1276
      • 17.8.5.3 T0CTL Register (Offset = 8h) [reset = X]

        1278
      • 17.8.5.4 T0TARGET Register (Offset = Ch) [reset = X]

        1279
      • 17.8.5.5 T1TARGET Register (Offset = 10h) [reset = X]

        1280
      • 17.8.5.6 T1CTL Register (Offset = 14h) [reset = X]

        1281
    • 17.8.6 AUX_SMPH Registers

      1282
      • 17.8.6.1 SMPH0 Register (Offset = 0h) [reset = X]

        1283
      • 17.8.6.2 SMPH1 Register (Offset = 4h) [reset = X]

        1284
      • 17.8.6.3 SMPH2 Register (Offset = 8h) [reset = X]

        1285
      • 17.8.6.4 SMPH3 Register (Offset = Ch) [reset = X]

        1286
      • 17.8.6.5 SMPH4 Register (Offset = 10h) [reset = X]

        1287
      • 17.8.6.6 SMPH5 Register (Offset = 14h) [reset = X]

        1288
      • 17.8.6.7 SMPH6 Register (Offset = 18h) [reset = X]

        1289
      • 17.8.6.8 SMPH7 Register (Offset = 1Ch) [reset = X]

        1290
      • 17.8.6.9 AUTOTAKE Register (Offset = 20h) [reset = X]

        1291
    • 17.8.7 AUX_ANAIF Registers

      1292
      • 17.8.7.1 ADCCTL Register (Offset = 10h) [reset = X]

        1293
      • 17.8.7.2 ADCFIFOSTAT Register (Offset = 14h) [reset = X]

        1295
      • 17.8.7.3 ADCFIFO Register (Offset = 18h) [reset = X]

        1296
      • 17.8.7.4 ADCTRIG Register (Offset = 1Ch) [reset = X]

        1297
      • 17.8.7.5 ISRCCTL Register (Offset = 20h) [reset = X]

        1298
    • 17.8.8 ADI_4_AUX Registers

      1299
      • 17.8.8.1 MUX0 Register (Offset = 0h) [reset = X]

        1300
      • 17.8.8.2 MUX1 Register (Offset = 1h) [reset = X]

        1301
      • 17.8.8.3 MUX2 Register (Offset = 2h) [reset = X]

        1302
      • 17.8.8.4 MUX3 Register (Offset = 3h) [reset = X]

        1303
      • 17.8.8.5 ISRC Register (Offset = 4h) [reset = X]

        1304
      • 17.8.8.6 COMP Register (Offset = 5h) [reset = X]

        1305
      • 17.8.8.7 MUX4 Register (Offset = 7h) [reset = X]

        1306
      • 17.8.8.8 ADC0 Register (Offset = 8h) [reset = X]

        1307
      • 17.8.8.9 ADC1 Register (Offset = 9h) [reset = X]

        1308
      • 17.8.8.10 ADCREF0 Register (Offset = Ah) [reset = X]

        1309
      • 17.8.8.11 ADCREF1 Register (Offset = Bh) [reset = X]

        1310
• 18 Battery Monitor and Temperature Sensor

  1311
  • 18.1 Introduction

    1312
  • 18.2 Functional Description

    1312
  • 18.3 BATMON Registers

    1312
    • 18.3.1 AON_BATMON Registers

      1313
      • 18.3.1.1 CTL Register (Offset = 0h) [reset = X]

        1314
      • 18.3.1.2 MEASCFG Register (Offset = 4h) [reset = X]

        1315
      • 18.3.1.3 TEMPP0 Register (Offset = Ch) [reset = X]

        1316
      • 18.3.1.4 TEMPP1 Register (Offset = 10h) [reset = X]

        1317
      • 18.3.1.5 TEMPP2 Register (Offset = 14h) [reset = X]

        1318
      • 18.3.1.6 BATMONP0 Register (Offset = 18h) [reset = X]

        1319
      • 18.3.1.7 BATMONP1 Register (Offset = 1Ch) [reset = X]

        1320
      • 18.3.1.8 IOSTRP0 Register (Offset = 20h) [reset = X]

        1321
      • 18.3.1.9 FLASHPUMPP0 Register (Offset = 24h) [reset = X]

        1322
      • 18.3.1.10 BAT Register (Offset = 28h) [reset = X]

        1323
      • 18.3.1.11 BATUPD Register (Offset = 2Ch) [reset = X]

        1324
      • 18.3.1.12 TEMP Register (Offset = 30h) [reset = X]

        1325
      • 18.3.1.13 TEMPUPD Register (Offset = 34h) [reset = X]

        1326
• 19 Universal Asynchronous Receivers and Transmitters (UARTS)

  1327
  • 19.1 Universal Asynchronous Receiver/Transmitter

    1328
  • 19.2 Block Diagram

    1329
  • 19.3 Signal Description

    1329
  • 19.4 Functional DescriptionFunctional Description section

    1329
    • 19.4.1 Transmit and Receive Logic

      1330
    • 19.4.2 Baud-Rate Generation

      1330
    • 19.4.3 Data Transmission

      1330
    • 19.4.4 Modem Handshake Support

      1331
      • 19.4.4.1 Signaling

        1331
      • 19.4.4.2 Flow Control

        1331
        • 19.4.4.2.1 Hardware Flow Control (RTS and CTS)

          1331
        • 19.4.4.2.2 Software Flow Control (Modem Status Interrupts)

          1331
    • 19.4.5 FIFO Operation

      1332
    • 19.4.6 Interrupts

      1332
    • 19.4.7 Loopback Operation

      1333
  • 19.5 Interface to DMA

    1333
  • 19.6 Initialization and Configuration

    1334
  • 19.7 UARTS Registers

    1335
    • 19.7.1 UART Registers

      1336
      • 19.7.1.1 DR Register (Offset = 0h) [reset = X]

        1337
      • 19.7.1.2 RSR Register (Offset = 4h) [reset = X]

        1338
      • 19.7.1.3 ECR Register (Offset = 4h) [reset = X]

        1339
      • 19.7.1.4 FR Register (Offset = 18h) [reset = X]

        1340
      • 19.7.1.5 IBRD Register (Offset = 24h) [reset = X]

        1341
      • 19.7.1.6 FBRD Register (Offset = 28h) [reset = X]

        1342
      • 19.7.1.7 LCRH Register (Offset = 2Ch) [reset = X]

        1343
      • 19.7.1.8 CTL Register (Offset = 30h) [reset = X]

        1344
      • 19.7.1.9 IFLS Register (Offset = 34h) [reset = X]

        1345
      • 19.7.1.10 IMSC Register (Offset = 38h) [reset = X]

        1346
      • 19.7.1.11 RIS Register (Offset = 3Ch) [reset = X]

        1348
      • 19.7.1.12 MIS Register (Offset = 40h) [reset = X]

        1350
      • 19.7.1.13 ICR Register (Offset = 44h) [reset = 0h]

        1351
      • 19.7.1.14 DMACTL Register (Offset = 48h) [reset = X]

        1352
• 20 Synchronous Serial Interface (SSI)

  1353
  • 20.1 Synchronous Serial Interface

    1354
  • 20.2 Block Diagram

    1355
  • 20.3 Signal Description

    1356
  • 20.4 Functional Description

    1356
    • 20.4.1 Bit Rate Generation

      1356
    • 20.4.2 FIFO Operation

      1356
      • 20.4.2.1 Transmit FIFO

        1356
      • 20.4.2.2 Receive FIFO

        1357
    • 20.4.3 Interrupts

      1357
    • 20.4.4 Frame Formats

      1358
      • 20.4.4.1 Texas Instruments Synchronous Serial Frame Format

        1358
      • 20.4.4.2 Motorola SPI Frame Format

        1359
        • 20.4.4.2.1 SPO Clock Polarity Bit

          1359
        • 20.4.4.2.2 SPH Phase-Control Bit

          1359
      • 20.4.4.3 Motorola SPI Frame Format With SPO = 0 and SPH = 0

        1359
      • 20.4.4.4 Motorola SPI Frame Format With SPO = 0 and SPH = 1

        1360
      • 20.4.4.5 Motorola SPI Frame Format With SPO = 1 and SPH = 0

        1361
      • 20.4.4.6 Motorola SPI Frame Format With SPO = 1 and SPH = 1

        1361
      • 20.4.4.7 MICROWIRE Frame Format

        1362
  • 20.5 DMA Operation

    1364
  • 20.6 Initialization and Configuration

    1365
  • 20.7 SSI Registers

    1366
    • 20.7.1 SSI Registers

      1367
      • 20.7.1.1 CR0 Register (Offset = 0h) [reset = X]

        1368
      • 20.7.1.2 CR1 Register (Offset = 4h) [reset = X]

        1369
      • 20.7.1.3 DR Register (Offset = 8h) [reset = X]

        1370
      • 20.7.1.4 SR Register (Offset = Ch) [reset = X]

        1371
      • 20.7.1.5 CPSR Register (Offset = 10h) [reset = X]

        1372
      • 20.7.1.6 IMSC Register (Offset = 14h) [reset = X]

        1373
      • 20.7.1.7 RIS Register (Offset = 18h) [reset = X]

        1374
      • 20.7.1.8 MIS Register (Offset = 1Ch) [reset = X]

        1375
      • 20.7.1.9 ICR Register (Offset = 20h) [reset = X]

        1376
      • 20.7.1.10 DMACR Register (Offset = 24h) [reset = X]

        1377
• 21 Inter-Integrated Circuit (I2C) Interface

  1378
  • 21.1 Inter-Integrated Circuit Interface

    1379
  • 21.2 Block Diagram

    1379
  • 21.3 Functional Description

    1379
    • 21.3.1 I2C Bus Functional Overview

      1380
      • 21.3.1.1 Start and Stop Conditions

        1380
      • 21.3.1.2 Data Format With 7-Bit Address

        1381
      • 21.3.1.3 Data Validity

        1381
      • 21.3.1.4 Acknowledge

        1381
      • 21.3.1.5 Arbitration

        1382
    • 21.3.2 Available Speed Modes

      1382
      • 21.3.2.1 Standard and Fast Modes

        1382
    • 21.3.3 Interrupts

      1382
      • 21.3.3.1 I2C Master Interrupts

        1383
      • 21.3.3.2 I2C Slave Interrupts

        1383
    • 21.3.4 Loopback Operation

      1383
    • 21.3.5 Command Sequence Flow Charts

      1383
      • 21.3.5.1 I2C Master Command Sequences

        1384
      • 21.3.5.2 I2C Slave Command Sequences

        1390
  • 21.4 Initialization and Configuration

    1391
  • 21.5 I2C Registers

    1391
    • 21.5.1 I2C Registers

      1392
      • 21.5.1.1 SOAR Register (Offset = 0h) [reset = X]

        1393
      • 21.5.1.2 SSTAT Register (Offset = 4h) [reset = X]

        1394
      • 21.5.1.3 SCTL Register (Offset = 4h) [reset = X]

        1395
      • 21.5.1.4 SDR Register (Offset = 8h) [reset = X]

        1396
      • 21.5.1.5 SIMR Register (Offset = Ch) [reset = X]

        1397
      • 21.5.1.6 SRIS Register (Offset = 10h) [reset = X]

        1398
      • 21.5.1.7 SMIS Register (Offset = 14h) [reset = X]

        1399
      • 21.5.1.8 SICR Register (Offset = 18h) [reset = X]

        1400
      • 21.5.1.9 MSA Register (Offset = 800h) [reset = X]

        1401
      • 21.5.1.10 MSTAT Register (Offset = 804h) [reset = X]

        1402
      • 21.5.1.11 MCTRL Register (Offset = 804h) [reset = X]

        1403
      • 21.5.1.12 MDR Register (Offset = 808h) [reset = X]

        1404
      • 21.5.1.13 MTPR Register (Offset = 80Ch) [reset = X]

        1405
      • 21.5.1.14 MIMR Register (Offset = 810h) [reset = X]

        1406
      • 21.5.1.15 MRIS Register (Offset = 814h) [reset = X]

        1407
      • 21.5.1.16 MMIS Register (Offset = 818h) [reset = X]

        1408
      • 21.5.1.17 MICR Register (Offset = 81Ch) [reset = X]

        1409
      • 21.5.1.18 MCR Register (Offset = 820h) [reset = X]

        1410
• 22 Integrated Interchip Sound (I2S) Module

  1411
  • 22.1 Introduction

    1412
  • 22.2 Digital Audio Interface

    1412
  • 22.3 Frame Configuration

    1413
  • 22.4 Pin Configuration

    1413
  • 22.5 Clock Configuration

    1413
    • 22.5.1 WCLK, BCLK, and MCLK Division Ratio

      1414
  • 22.6 Serial Interface Formats

    1414
    • 22.6.1 I2S

      1414
    • 22.6.2 Left Justified (LJF)

      1415
    • 22.6.3 Right Justified (RJF)

      1415
    • 22.6.4 DSP

      1416
  • 22.7 Memory Interface

    1417
    • 22.7.1 Word Lengths

      1417
    • 22.7.2 Audio Channels

      1417
    • 22.7.3 Memory Buffers and Pointers

      1418
  • 22.8 Samplestamp Generator

    1418
    • 22.8.1 Counters and Registers

      1419
    • 22.8.2 Starting Input and Output Pins

      1420
    • 22.8.3 Samplestamp Capturing

      1420
  • 22.9 Usage

    1421
    • 22.9.1 Start-up Sequence

      1421
    • 22.9.2 Termination Sequence

      1422
  • 22.10 I2S Registers

    1422
    • 22.10.1 I2S Registers

      1423
      • 22.10.1.1 AIFWCLKSRC Register (Offset = 0h) [reset = X]

        1424
      • 22.10.1.2 AIFDMACFG Register (Offset = 4h) [reset = X]

        1425
      • 22.10.1.3 AIFDIRCFG Register (Offset = 8h) [reset = X]

        1426
      • 22.10.1.4 AIFFMTCFG Register (Offset = Ch) [reset = X]

        1427
      • 22.10.1.5 AIFWMASK0 Register (Offset = 10h) [reset = X]

        1428
      • 22.10.1.6 AIFWMASK1 Register (Offset = 14h) [reset = X]

        1429
      • 22.10.1.7 AIFWMASK2 Register (Offset = 18h) [reset = X]

        1430
      • 22.10.1.8 AIFPWMVALUE Register (Offset = 1Ch) [reset = X]

        1431
      • 22.10.1.9 AIFINPTRNEXT Register (Offset = 20h) [reset = X]

        1432
      • 22.10.1.10 AIFINPTR Register (Offset = 24h) [reset = X]

        1433
      • 22.10.1.11 AIFOUTPTRNEXT Register (Offset = 28h) [reset = X]

        1434
      • 22.10.1.12 AIFOUTPTR Register (Offset = 2Ch) [reset = X]

        1435
      • 22.10.1.13 STMPCTL Register (Offset = 34h) [reset = X]

        1436
      • 22.10.1.14 STMPXCNTCAPT0 Register (Offset = 38h) [reset = X]

        1437
      • 22.10.1.15 STMPXPER Register (Offset = 3Ch) [reset = X]

        1438
      • 22.10.1.16 STMPWCNTCAPT0 Register (Offset = 40h) [reset = X]

        1439
      • 22.10.1.17 STMPWPER Register (Offset = 44h) [reset = X]

        1440
      • 22.10.1.18 STMPINTRIG Register (Offset = 48h) [reset = X]

        1441
      • 22.10.1.19 STMPOUTTRIG Register (Offset = 4Ch) [reset = X]

        1442
      • 22.10.1.20 STMPWSET Register (Offset = 50h) [reset = X]

        1443
      • 22.10.1.21 STMPWADD Register (Offset = 54h) [reset = X]

        1444
      • 22.10.1.22 STMPXPERMIN Register (Offset = 58h) [reset = X]

        1445
      • 22.10.1.23 STMPWCNT Register (Offset = 5Ch) [reset = X]

        1446
      • 22.10.1.24 STMPXCNT Register (Offset = 60h) [reset = X]

        1447
      • 22.10.1.25 STMPXCNTCAPT1 Register (Offset = 64h) [reset = X]

        1448
      • 22.10.1.26 STMPWCNTCAPT1 Register (Offset = 68h) [reset = X]

        1449
      • 22.10.1.27 IRQMASK Register (Offset = 70h) [reset = X]

        1450
      • 22.10.1.28 IRQFLAGS Register (Offset = 74h) [reset = X]

        1451
      • 22.10.1.29 IRQSET Register (Offset = 78h) [reset = X]

        1452
      • 22.10.1.30 IRQCLR Register (Offset = 7Ch) [reset = X]

        1453
• 23 Radio

  1454
  • 23.1 RF Core

    1455
    • 23.1.1 High-Level Description and Overview

      1455
  • 23.2 Radio Doorbell

    1456
    • 23.2.1 Operational Description

      1457
  • 23.3 RF Core HAL

    1457
    • 23.3.1 Hardware Support

      1457
    • 23.3.2 Firmware Support

      1457
      • 23.3.2.1 Commands

        1458
      • 23.3.2.2 Command Status

        1459
      • 23.3.2.3 Interrupts

        1461
      • 23.3.2.4 Passing Data

        1461
      • 23.3.2.5 Command Scheduling

        1461
        • 23.3.2.5.1 Triggers

          1462
        • 23.3.2.5.2 Conditional Execution

          1463
        • 23.3.2.5.3 Handling Before Start of Command

          1464
      • 23.3.2.6 Command Data Structures

        1464
        • 23.3.2.6.1 Radio Operation Command Structure

          1465
      • 23.3.2.7 Data Entry Structures

        1465
        • 23.3.2.7.1 Data Entry Queue

          1465
        • 23.3.2.7.2 Data Entry

          1466
        • 23.3.2.7.3 Pointer Entry

          1467
        • 23.3.2.7.4 RX Multi-Element Entry

          1467
      • 23.3.2.8 External Signaling

        1468
    • 23.3.3 Command Definitions

      1468
      • 23.3.3.1 Protocol-Independent Radio Operation Commands

        1468
        • 23.3.3.1.1 CMD_NOP: No Operation Command

          1469
        • 23.3.3.1.2 CMD_RADIO_SETUP: Set Up Radio Settings Command

          1469
        • 23.3.3.1.3 CMD_FS_POWERUP: Power-Up Frequency Synthesizer

          1474
        • 23.3.3.1.4 CMD_FS_POWERDOWN: Power Down Frequency Synthesizer

          1474
        • 23.3.3.1.5 CMD_FS: Frequency Synthesizer Controls Command

          1474
        • 23.3.3.1.6 CMD_FS_OFF: Turn Off Frequency Synthesizer

          1475
        • 23.3.3.1.7 CMD_RX_TEST: Receiver Test Command

          1475
        • 23.3.3.1.8 CMD_TX_TEST: Transmitter Test Command

          1476
        • 23.3.3.1.9 CMD_SYNC_STOP_RAT: Synchronize and Stop Radio Timer Command

          1477
        • 23.3.3.1.10 CMD_SYNC_START_RAT: Synchronously Start Radio Timer Command

          1477
        • 23.3.3.1.11 CMD_COUNT: Counter Command

          1478
        • 23.3.3.1.12 CMD_SCH_IMM: Run Immediate Command as Radio Operation

          1478
        • 23.3.3.1.13 CMD_COUNT_BRANCH: Counter Command With Branch of Command Chain

          1479
        • 23.3.3.1.14 CMD_PATTERN_CHECK: Check a Value in Memory Against a Pattern

          1480
    • 23.3.4 Protocol-Independent Direct and Immediate Commands

      1481
      • 23.3.4.1 CMD_ABORT: Abort Command

        1481
      • 23.3.4.2 CMD_STOP: Stop Command

        1481
      • 23.3.4.3 CMD_GET_RSSI: Read RSSI Command

        1482
      • 23.3.4.4 CMD_UPDATE_RADIO_SETUP: Update Radio Settings Command

        1482
      • 23.3.4.5 CMD_TRIGGER: Generate Command Trigger

        1482
      • 23.3.4.6 CMD_GET_FW_INFO: Request Information on the Firmware Being Run

        1483
      • 23.3.4.7 CMD_START_RAT: Asynchronously Start Radio Timer Command

        1483
      • 23.3.4.8 CMD_PING: Respond With Interrupt

        1483
      • 23.3.4.9 CMD_SET_RAT_CMP: Set RAT Channel to Compare Mode

        1483
      • 23.3.4.10 CMD_SET_RAT_CPT: Set RAT Channel to Capture Mode

        1484
      • 23.3.4.11 CMD_DISABLE_RAT_CH: Disable RAT Channel

        1484
      • 23.3.4.12 CMD_SET_RAT_OUTPUT: Set RAT Output to a Specified Mode

        1485
      • 23.3.4.13 CMD_ARM_RAT_CH: Arm RAT Channel

        1485
      • 23.3.4.14 CMD_DISARM_RAT_CH: Disarm RAT Channel

        1486
      • 23.3.4.15 CMD_SET_TX_POWER: Set Transmit Power

        1486
      • 23.3.4.16 CMD_UPDATE_FS: Set New Synth Frequency Without Recalibration

        1486
      • 23.3.4.17 CMD_BUS_REQUEST: Request System BUS Available for RF Core

        1487
    • 23.3.5 Immediate Commands for Data Queue Manipulation

      1487
      • 23.3.5.1 CMD_ADD_DATA_ENTRY: Add Data Entry to Queue

        1487
      • 23.3.5.2 CMD_REMOVE_DATA_ENTRY: Remove First Data Entry From Queue

        1488
      • 23.3.5.3 CMD_FLUSH_QUEUE: Flush Queue

        1488
      • 23.3.5.4 CMD_CLEAR_RX: Clear All RX Queue Entries

        1489
      • 23.3.5.5 CMD_REMOVE_PENDING_ENTRIES: Remove Pending Entries From Queue

        1489
  • 23.4 Data Queue Usage

    1491
    • 23.4.1 Operations on Data Queues Only Available for Internal Radio CPU Operations

      1491
      • 23.4.1.1 PROC_ALLOCATE_TX: Allocate TX Entry for Reading

        1491
      • 23.4.1.2 PROC_FREE_DATA_ENTRY: Free Allocated Data Entry

        1491
      • 23.4.1.3 PROC_FINISH_DATA_ENTRY: Finish Use of First Data Entry From Queue

        1491
      • 23.4.1.4 PROC_ALLOCATE_RX: Allocate RX Buffer for Storing Data

        1492
      • 23.4.1.5 PROC_FINISH_RX: Commit Received Data to RX Data Entry

        1493
    • 23.4.2 Radio CPU Usage Model

      1493
      • 23.4.2.1 Receive Queues

        1493
      • 23.4.2.2 Transmit Queues

        1493
  • 23.5 IEEE 802.15.4

    1494
    • 23.5.1 IEEE 802.15.4 Commands

      1494
      • 23.5.1.1 IEEE 802.15.4 Radio Operation Command Structures

        1494
      • 23.5.1.2 IEEE 802.15.4 Immediate Command Structures

        1496
      • 23.5.1.3 Output Structures

        1497
      • 23.5.1.4 Other Structures and Bit Fields

        1498
    • 23.5.2 Interrupts

      1501
    • 23.5.3 Data Handling

      1501
      • 23.5.3.1 Receive Buffers

        1501
      • 23.5.3.2 Transmit Buffers

        1502
    • 23.5.4 Radio Operation Commands

      1502
      • 23.5.4.1 RX Operation

        1503
        • 23.5.4.1.1 Frame Filtering and Source Matching

          1504
        • 23.5.4.1.2 Frame Reception

          1505
        • 23.5.4.1.3 ACK Transmission

          1506
        • 23.5.4.1.4 End of Receive Operation

          1506
        • 23.5.4.1.5 CCA Monitoring

          1507
      • 23.5.4.2 Energy Detect Scan Operation

        1508
      • 23.5.4.3 CSMA-CA Operation

        1508
      • 23.5.4.4 Transmit Operation

        1511
      • 23.5.4.5 Receive Acknowledgment Operation

        1512
      • 23.5.4.6 Abort Background-Level Operation Command

        1513
      • 23.5.4.7 Update Radio Settings Command

        1513
    • 23.5.5 Immediate Commands

      1514
      • 23.5.5.1 Modify CCA Parameter Command

        1514
      • 23.5.5.2 Modify Frame-Filtering Parameter Command

        1514
      • 23.5.5.3 Enable or Disable Source Matching Entry Command

        1514
      • 23.5.5.4 Abort Foreground-Level Operation Command

        1515
      • 23.5.5.5 Stop Foreground-Level Operation Command

        1515
      • 23.5.5.6 Request CCA and RSSI Information Command

        1515
  • 23.6 Bluetooth Low Energy

    1515
    • 23.6.1 Bluetooth Low Energy Commands

      1515
      • 23.6.1.1 Command Data Definitions

        1516
        • 23.6.1.1.1 BLE Command Structures

          1516
      • 23.6.1.2 Parameter Structures

        1517
      • 23.6.1.3 Output Structures

        1520
      • 23.6.1.4 Other Structures and Bit Fields

        1522
    • 23.6.2 Interrupts

      1524
    • 23.6.3 Data Handling

      1524
      • 23.6.3.1 Receive Buffers

        1525
      • 23.6.3.2 Transmit Buffers

        1525
    • 23.6.4 Radio Operation Command Descriptions

      1525
      • 23.6.4.1 Link Layer Connection

        1527
      • 23.6.4.2 Slave Command

        1530
      • 23.6.4.3 Master Command

        1530
      • 23.6.4.4 Advertiser

        1531
        • 23.6.4.4.1 Connectable Undirected-Advertiser Command

          1534
        • 23.6.4.4.2 Connectable Directed-Advertiser Command

          1534
        • 23.6.4.4.3 Non-Connectable Advertiser Command

          1535
        • 23.6.4.4.4 Scannable Undirected-Advertiser Command

          1535
      • 23.6.4.5 Scanner Command

        1536
      • 23.6.4.6 Initiator Command

        1540
      • 23.6.4.7 Generic Receiver Command

        1542
      • 23.6.4.8 PHY Test Transmit Command

        1544
      • 23.6.4.9 White List Processing

        1545
    • 23.6.5 Immediate Commands

      1546
      • 23.6.5.1 Update Advertising Payload Command

        1546
  • 23.7 Radio Registers

    1546
    • 23.7.1 RFC_DBELL Registers

      1547
      • 23.7.1.1 CMDR Register (Offset = 0h) [reset = X]

        1548
      • 23.7.1.2 CMDSTA Register (Offset = 4h) [reset = X]

        1549
      • 23.7.1.3 RFHWIFG Register (Offset = 8h) [reset = X]

        1550
      • 23.7.1.4 RFHWIEN Register (Offset = Ch) [reset = X]

        1552
      • 23.7.1.5 RFCPEIFG Register (Offset = 10h) [reset = X]

        1553
      • 23.7.1.6 RFCPEIEN Register (Offset = 14h) [reset = FFFFFFFFh]

        1556
      • 23.7.1.7 RFCPEISL Register (Offset = 18h) [reset = X]

        1558
      • 23.7.1.8 RFACKIFG Register (Offset = 1Ch) [reset = X]

        1561
      • 23.7.1.9 SYSGPOCTL Register (Offset = 20h) [reset = X]

        1562
    • 23.7.2 RFC_PWR Registers

      1565
      • 23.7.2.1 PWMCLKEN Register (Offset = 0h) [reset = X]

        1566
    • 23.7.3 RFC_RAT Registers

      1568
      • 23.7.3.1 RATCNT Register (Offset = 4h) [reset = X]

        1569
• Important Notice

  1570