Texas Instruments CC2650DK ユーザーズマニュアル
µDMA Registers
12.5.1.5 WAITONREQ Register (Offset = 10h) [reset = FFFF1EFFh]
WAITONREQ is shown in
and described in
Channel Wait On Request Status
Figure 12-11. WAITONREQ Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
CHNLSTATUS
R-FFFF1EFFh
Table 12-12. WAITONREQ Register Field Descriptions
Bit
Field
Type
Reset
Description
31-0
CHNLSTATUS
R
FFFF1EFFh Channel wait on request status: Bit [Ch] = 0: Once uDMA receives a
single or burst request on channel Ch, this channel may come out of
active state even if request is still present. Bit [Ch] = 1: Once uDMA
receives a single or burst request on channel Ch, it keeps channel
Ch in active state until the requests are deasserted. This handshake
is necessary for channels where the requester is in an asynchronous
domain or can run at slower clock speed than uDMA
active state even if request is still present. Bit [Ch] = 1: Once uDMA
receives a single or burst request on channel Ch, it keeps channel
Ch in active state until the requests are deasserted. This handshake
is necessary for channels where the requester is in an asynchronous
domain or can run at slower clock speed than uDMA
1058
Micro Direct Memory Access (µDMA)
SWCU117A – February 2015 – Revised March 2015
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