Texas Instruments CC2650DK ユーザーズマニュアル
Initialization and Configuration
In one-shot mode, the timer stops counting after the time-out event. To re-enable the timer, repeat the
sequence. A timer configured in periodic mode reloads the timer and continues counting after the time-out
event.
sequence. A timer configured in periodic mode reloads the timer and continues counting after the time-out
event.
13.4.2 Input Edge-Count Mode
A timer is configured to Input Edge-Count mode by the following sequence:
1. Ensure the timer is disabled (the TAEN bit is cleared) before making any changes.
2. Write the GPTM Configuration [GPT_CFG] register with a value of 0x0000.0004.
3. In the GPTM Timer Mode [GPT_TnMR] register, write the TnCMR field to 0x0 and the TnMR field to
0x3.
4. Configure the type of events that the timer captures by writing the TnEVENT field of the GPTM Control
[GPT_CTL] register.
5. If a prescaler is to be used, write the prescale value to the GPTM Timer n Prescale Register
[GPT_TnPR].
6. Load the timer start value into the GPTM Timer n Interval Load [GPT_TnILR] register.
7. Load the event count into the GPTM Timer n Match [GPT_TnMATCHR] register.
8. If interrupts are required, set the CnMIM bit in the GPTM Interrupt Mask [GPT_IMR] register.
9. Set the TnEN bit in the [GPT_CTL] register to enable the timer and begin waiting for edge events.
10. Poll the CnMRIS bit in the [GPT_RIS] register, or wait for the interrupt to be generated (if enabled). In
both cases, the status flags are cleared by writing a 1 to the CnMCINT bit of the GPTM Interrupt Clear
[GPT_ICR] register.
[GPT_ICR] register.
When counting down in input edge-count mode, the timer stops after the programmed number of edge
events has been detected. To re-enable the timer, ensure that the TnEN bit is cleared and repeat steps 4
through 9.
events has been detected. To re-enable the timer, ensure that the TnEN bit is cleared and repeat steps 4
through 9.
13.4.3 Input Edge-Timing Mode
A timer is configured to Input Edge-Timing mode by the following sequence:
1. Ensure the timer is disabled (the TAEN bit is cleared) before making any changes.
2. Write the GPTM Configuration [GPT_CFG] register with a value of 0x0000.0004.
3. In the GPTM Timer Mode [GPT_TnMR] register, write the TnCM field to 0x1 and the TnMR field to
0x3.
4. Configure the type of events that the timer captures by writing the TnEVENT field of the GPTM Control
[GPT_CTL] register.
5. If a prescaler is to be used, write the prescale value to the GPTM Timer n Prescale Register
[GPT_TnPR].
6. Load the timer start value into the GPTM Timer n Interval Load [GPT_TnILR] register.
7. If interrupts are required, set the CnMIMbit in the GPTM Interrupt Mask [GPT_IMR] register.
8. Set the TnEN bit in the [GPT_CTL] register to enable the timer and start counting.
9. Poll the CnMRIS bit in the [GPT_RIS] register, or wait for the interrupt to be generated (if enabled). In
both cases, the status flags are cleared by writing a 1 to the CnMCINT bit of the GPTM Interrupt Clear
[GPT_ICR] register.
[GPT_ICR] register.
In input edge timing mode, the timer continues running after an edge event has been detected, but the
timer interval can be changed at any time by writing the [GPT_TnILR] register. The change takes effect at
the next cycle after the write.
timer interval can be changed at any time by writing the [GPT_TnILR] register. The change takes effect at
the next cycle after the write.
1085
SWCU117A – February 2015 – Revised March 2015
Timers
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