Texas Instruments CC2650DK ユーザーズマニュアル
General-Purpose Timer Registers
13.5.1.28 ADCEV Register (Offset = 70h) [reset = X]
ADCEV is shown in
and described in
ADC Event This register allows software to enable/disable GPT ADC trigger events.
Figure 13-36. ADCEV Register
31
30
29
28
27
26
25
24
RESERVED
R-X
23
22
21
20
19
18
17
16
RESERVED
R-X
15
14
13
12
11
10
9
8
RESERVED
TBMADCEN
CBEADCEN
CBMADCEN
TBTOADCEN
R-X
R/W-X
R/W-X
R/W-X
R/W-X
7
6
5
4
3
2
1
0
RESERVED
TAMADCEN
RTCADCEN
CAEADCEN
CAMADCEN
TATOADCEN
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
Table 13-35. ADCEV Register Field Descriptions
Bit
Field
Type
Reset
Description
31-12
RESERVED
R
X
Software should not rely on the value of a reserved field. Writing any
other value may result in undefined behavior.
other value may result in undefined behavior.
11
TBMADCEN
R/W
X
GPT Timer B Match ADC Trigger Enable
10
CBEADCEN
R/W
X
GPT Timer B Capture Event ADC Trigger Enable
9
CBMADCEN
R/W
X
GPT Timer B Capture Match ADC Trigger Enable
8
TBTOADCEN
R/W
X
GPT Timer B Time-Out ADC Trigger Enable
7-5
RESERVED
R/W
X
Software should not rely on the value of a reserved field. Writing any
other value may result in undefined behavior.
other value may result in undefined behavior.
4
TAMADCEN
R/W
X
GPT Timer A Match ADC Trigger Enable
3
RTCADCEN
R/W
X
GPT RTC Match ADC Trigger Enable
2
CAEADCEN
R/W
X
GPT Timer A Capture Event ADC Trigger Enable
1
CAMADCEN
R/W
X
GPT Timer A Capture Match ADC Trigger Enable
0
TATOADCEN
R/W
X
GPT Timer A Time-Out ADC Trigger Enable
1121
SWCU117A – February 2015 – Revised March 2015
Timers
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