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UARTS Registers
19.7.1.14 DMACTL Register (Offset = 48h) [reset = X]
DMACTL is shown in
and described in
DMA Control
Figure 19-17. DMACTL Register
31
30
29
28
27
26
25
24
RESERVED
R/W-X
23
22
21
20
19
18
17
16
RESERVED
R/W-X
15
14
13
12
11
10
9
8
RESERVED
R/W-X
7
6
5
4
3
2
1
0
RESERVED
DMAONERR
TXDMAE
RXDMAE
R/W-X
R/W-X
R/W-X
R/W-X
Table 19-17. DMACTL Register Field Descriptions
Bit
Field
Type
Reset
Description
31-3
RESERVED
R/W
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
2
DMAONERR
R/W
X
DMA on error. If this bit is set to 1, the DMA receive request outputs
(for single and burst requests) are disabled when the UART error
interrupt is asserted (more specifically if any of the error interrupts
RIS.PERIS, RIS.BERIS, RIS.FERIS or RIS.OERIS are asserted).
(for single and burst requests) are disabled when the UART error
interrupt is asserted (more specifically if any of the error interrupts
RIS.PERIS, RIS.BERIS, RIS.FERIS or RIS.OERIS are asserted).
1
TXDMAE
R/W
X
Transmit DMA enable. If this bit is set to 1, DMA for the transmit
FIFO is enabled.
FIFO is enabled.
0
RXDMAE
R/W
X
Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO
is enabled.
is enabled.
1352
Universal Asynchronous Receivers and Transmitters (UARTS)
SWCU117A – February 2015 – Revised March 2015
Copyright © 2015, Texas Instruments Incorporated