Texas Instruments CC2650DK ユーザーズマニュアル
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SSI Registers
Assuming the system clock is 48 MHz, the bit rate calculation is shown in
.
SSIn_CLK = PERDMACLK / (CPSDVSR × (1 + SCR)) 1 × 106 = 20 × 106 / (CPSDVSR × (1 + SCR))1000000
bps = 48000000 Hz / (2 × (1 + 23))
bps = 48000000 Hz / (2 × (1 + 23))
(6)
In this case, if CPSDVSR = 0x2, SCR must be 0x18.
The configuration sequence is:
1. Ensure that the SSE bit in the [SSI_CR1] register is clear.
2. Write the [SSI_CR1] register with a value of 0x0000 0000.
3. Write the [SSI_CPSR] register with a value of 0x0000 0002.
4. Write the [SSI_CR0] register with a value of 0x0000 1817.
5. The SSI is then enabled by setting the SSE bit in the [SSI_CR1] register.
20.7 SSI Registers
1366
Synchronous Serial Interface (SSI)
SWCU117A – February 2015 – Revised March 2015
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