Texas Instruments CC2650DK ユーザーズマニュアル
Change
of data
allow
Data line
stable
SDA
SCL
R/S
LSB
Slave address
MSB
Data
Slave address
ACK
LSB
MSB
ACK
R/S
LSB
MSB
SDA
SCL
1
2
7
8
9
1
2
7
8
9
Stop
Start
Functional Description
21.3.1.2 Data Format With 7-Bit Address
Data transfers follow the format shown in
. After the Start condition, a slave address is
transmitted. This address is 7 bits long followed by an eighth bit, which is a data direction bit (the R/S bit
in the [I2C_MSA] register). If the RS bit is clear, it indicates a transmit operation (send), and if it is set, it
indicates a request for data (receive). A data transfer is always terminated by a Stop condition generated
by the master; however, a master can initiate communications with another device on the bus, by
generating a Repeated Start condition and addressing another slave without first generating a Stop
condition. Various combinations of receive and transmit formats are then possible within a single transfer.
in the [I2C_MSA] register). If the RS bit is clear, it indicates a transmit operation (send), and if it is set, it
indicates a request for data (receive). A data transfer is always terminated by a Stop condition generated
by the master; however, a master can initiate communications with another device on the bus, by
generating a Repeated Start condition and addressing another slave without first generating a Stop
condition. Various combinations of receive and transmit formats are then possible within a single transfer.
Figure 21-4. Complete Data Transfer With a 7-Bit Address
The first 7 bits of the first byte comprise the slave address (see
). The eighth bit determines
the direction of the message. A 0 in the R/S position of the first byte means that the master transmits
(sends) data to the selected slave, and a 1 in this position means that the master receives data from the
slave.
(sends) data to the selected slave, and a 1 in this position means that the master receives data from the
slave.
Figure 21-5. R/S Bit in First Byte
21.3.1.3 Data Validity
The SDA line must contain stable data during the high period of the clock, and the data line can change
only when SCL is low (see
only when SCL is low (see
Figure 21-6. Data Validity During Bit Transfer on the I
2
C Bus
21.3.1.4 Acknowledge
All bus transactions have a required acknowledge clock cycle generated by the master. During the
acknowledge cycle, the transmitter (master or slave) releases the SDA line. To acknowledge the
transaction, the receiver must pull down SDA during the acknowledge clock cycle. The data transmitted by
the receiver during the acknowledge cycle must comply with the data validity requirements described in
acknowledge cycle, the transmitter (master or slave) releases the SDA line. To acknowledge the
transaction, the receiver must pull down SDA during the acknowledge clock cycle. The data transmitted by
the receiver during the acknowledge cycle must comply with the data validity requirements described in
, Data Validity.
When a slave receiver does not acknowledge the slave address, the slave must leave SDA high so that
the master can generate a Stop condition and abort the current transfer. If the master device is acting as a
receiver during a transfer, it is responsible for acknowledging each transfer made by the slave. Because
the master controls the number of bytes in the transfer, it signals the end of data to the slave transmitter
by not generating an acknowledge on the last data byte. The slave transmitter must then release SDA to
let the master generate a Stop or a Repeated Start condition.
the master can generate a Stop condition and abort the current transfer. If the master device is acting as a
receiver during a transfer, it is responsible for acknowledging each transfer made by the slave. Because
the master controls the number of bytes in the transfer, it signals the end of data to the slave transmitter
by not generating an acknowledge on the last data byte. The slave transmitter must then release SDA to
let the master generate a Stop or a Repeated Start condition.
1381
SWCU117A – February 2015 – Revised March 2015
Inter-Integrated Circuit (I
2
C) Interface
Copyright © 2015, Texas Instruments Incorporated