Texas Instruments CC2650DK ユーザーズマニュアル
I
2
C Registers
21.5.1 I2C Registers
lists the memory-mapped registers for the I2C. All register offset addresses not listed in
should be considered as reserved locations and the register contents should not be modified.
Table 21-2. I2C Registers
Offset
Acronym
Register Name
Section
0h
SOAR
Slave Own Address
4h
SSTAT
Slave Status
4h
SCTL
Slave Control
8h
SDR
Slave Data
Ch
SIMR
Slave Interrupt Mask
10h
SRIS
Slave Raw Interrupt Status
14h
SMIS
Slave Masked Interrupt Status
18h
SICR
Slave Interrupt Clear
800h
MSA
Master Salve Address
804h
MSTAT
Master Status
804h
MCTRL
Master Control
808h
MDR
Master Data
80Ch
MTPR
I2C Master Timer Period
810h
MIMR
Master Interrupt Mask
814h
MRIS
Master Raw Interrupt Status
818h
MMIS
Master Masked Interrupt Status
81Ch
MICR
Master Interrupt Clear
820h
MCR
Master Configuration
1392
SWCU117A – February 2015 – Revised March 2015
Inter-Integrated Circuit (I
2
C) Interface
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