Texas Instruments CC2650DK ユーザーズマニュアル
I
2
C Registers
21.5.1.15 MRIS Register (Offset = 814h) [reset = X]
MRIS is shown in
and described in
Master Raw Interrupt Status This register show the unmasked interrupt status.
Figure 21-28. MRIS Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESERVED
R-X
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESERVED
RIS
R-X
R-X
Table 21-17. MRIS Register Field Descriptions
Bit
Field
Type
Reset
Description
31-1
RESERVED
R
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
0
RIS
R
X
Raw interrupt status 0: No interrupt 1: A master interrupt is pending.
This bit is cleared by writing 1 to the MICR.IC bit .
This bit is cleared by writing 1 to the MICR.IC bit .
1407
SWCU117A – February 2015 – Revised March 2015
Inter-Integrated Circuit (I
2
C) Interface
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