Texas Instruments CC2650DK ユーザーズマニュアル
I2S Registers
22.10.1.4 AIFFMTCFG Register (Offset = Ch) [reset = X]
AIFFMTCFG is shown in
and described in
Serial Interface Format Configuration
Figure 22-11. AIFFMTCFG Register
31
30
29
28
27
26
25
24
RESERVED
R-X
23
22
21
20
19
18
17
16
RESERVED
R-X
15
14
13
12
11
10
9
8
DATA_DELAY
R/W-1h
7
6
5
4
3
2
1
0
MEM_LEN_24
SMPL_EDGE
DUAL_PHASE
WORD_LEN
R/W-X
R/W-1h
R/W-1h
R/W-10h
Table 22-5. AIFFMTCFG Register Field Descriptions
Bit
Field
Type
Reset
Description
31-16
RESERVED
R
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
15-8
DATA_DELAY
R/W
1h
The number of BCLK periods between a WCLK edge and MSB of
the first word in a phase: 0x00: LJF format 0x01: I2S and DSP
format 0x02: RJF format ... 0xFF: RJF format Note: When 0, MSB of
the next word will be output in the idle period between LSB of the
previous word and the start of the next word. Otherwise logical 0 will
be output until the data delay has expired.
the first word in a phase: 0x00: LJF format 0x01: I2S and DSP
format 0x02: RJF format ... 0xFF: RJF format Note: When 0, MSB of
the next word will be output in the idle period between LSB of the
previous word and the start of the next word. Otherwise logical 0 will
be output until the data delay has expired.
7
MEM_LEN_24
R/W
X
The size of each word stored to or loaded from memory:
0h = 16BIT : 16-bit (one 16 bit access per sample)
1h = 24BIT : 24-bit (one 8 bit and one 16 bit locked access per
sample)
sample)
6
SMPL_EDGE
R/W
1h
On the serial audio interface, data (and wclk) is sampled and
clocked out on opposite edges of BCLK.
clocked out on opposite edges of BCLK.
0h = Data is sampled on the negative edge and clocked out on the
positive edge.
positive edge.
1h = Data is sampled on the positive edge and clocked out on the
negative edge.
negative edge.
5
DUAL_PHASE
R/W
1h
Selects dual- or single-phase format. 0: Single-phase 1: Dual-phase
4-0
WORD_LEN
R/W
10h
Number of bits per word (8-24): In single-phase format, this is the
exact number of bits per word. In dual-phase format, this is the
maximum number of bits per word. Values below 8 and above 24
give undefined behavior. Data written to memory is always aligned to
16 or 24 bits as defined by MEM_LEN_24. Bit widths that differ from
this alignment will either be truncated or zero padded.
exact number of bits per word. In dual-phase format, this is the
maximum number of bits per word. Values below 8 and above 24
give undefined behavior. Data written to memory is always aligned to
16 or 24 bits as defined by MEM_LEN_24. Bit widths that differ from
this alignment will either be truncated or zero padded.
1427
SWCU117A – February 2015 – Revised March 2015
Integrated Interchip Sound (I2S) Module
Copyright © 2015, Texas Instruments Incorporated